US4384342A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for reducing access time to plural memory modules using five present-fetch and one prefetch address registers
Assignee: Panafacom Ltd
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Filing: 1980-03-28
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Granted: 1983-05-17
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Expires: 2000-03-28
Abstract
Abstract A lookahead (guessahead) prefetching technique is used to reduce the average access time, for accessing memory modules when program addresses are modified into effective addresses for addressing the modules. A first memory address register stores the column address and module designation portions of the current effective address, a second memory address register stores the row address portion of the current effective address, and a third memory address register stores the module designation portion of the prior effective address. Since the same module is frequently accessed many times in succession, the average access time is reduced by starting an access based upon the contents of the second and third memory address registers without waiting until the column address and module designation portions of the current effective address are available for storage in the first memory address register. The access is completed, after the column address and module designation portions of the current effective address are determined, if a comparator which is connected to the first and third memory address registers confirms that the same memory module is being successively accessed. If not, the modules are accessed again based upon the contents of the first and second memory address modules.
Inventors
- 👤 Takao Imura
- 👤 Shigeru Koyanagi
- 👤 Yoshihiro Joda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:13
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0215
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
302 words
A system for accessing memory modules by using an effective address composed of first, second and third parts, the first and second parts being determined later than the third part, comprising: a first means for storing the first and second parts of a current effective address; a second means for storing the third part of said current effective address; a third means for storing the first part of the previous effective address; fourth means for comparing the first part of said current effective address stored in said first means with the first part of said previous effective address stored in said third means when the first and second parts of said current effective address are determined; and fifth means responsive to said first, second, third, and fourth means for accessing said memory modules by using the first part of said previous effective address stored in said third means and the third part of said current effective address stored in said second means to initiate an access before the first and second parts of the current effective address are available, said fifth means additionally comprising means for completing the access after the first and second parts of the current effective address are available by using the second part of said current effective address stored in said first means if the first parts of said previous and said current effective addresses are determined to be the same as each other by said fourth means, and for accessing another module by using the first and second parts of said current effective address stored in said first means and the third part of said current effective address stored in said second means if the first parts of said previous and said current effective addresses are determined to be different from each other by said fourth means.
Claim 2
Independent Claim
302 words
A system for accessing memory modules by using an effective address composed of first, second and third parts, the first and second parts being determined later than the third part, comprising: a first means for storing the first and second parts of a current effective address; a second means for storing the third part of said current effective address; a third means for storing the first part of the previous effective address; fourth means for comparing the first part of said current effective address stored in said first means with the first part of said previous effective address stored in said third means when the first and second parts of said current effective address are determined; and fifth means responsive to said first, second, third, and fourth means for accessing said memory modules by using the first part of said previous effective address stored in said third means and the third part of said current effective address stored in said second means to initiate an access before the first and second parts of the current effective address are available, said fifth means additionally comprising means for completing the access after the first and second parts of the current effective address are available by using the second part of said current effective address stored in said first means if the first parts of said previous and said current effective addresses are determined to be the same as each other by said fourth means, and for accessing another module by using the first and second parts of said current effective address stored in said first means and the third part of said current effective address stored in said second means if the first parts of said previous and said current effective addresses are determined to be different from each other by said fourth means.
Claim 3
Dependent Claim
47 words
A system as set forth in claim 1, further comprising a multiplexer means for transmitting the third part of said current effective address stored in said second means and the second part of said current effective address stored in said first means to said memory modules time-divisionally.
Claim 4
Dependent Claim
45 words
A system as set forth in claim 1, wherein the first part of said effective address designates the selection of said memory modules and the second and third parts of said effective address designate the selection of memory cells in each of said memory modules.
Claim 5
Dependent Claim
73 words
A system as set forth in claim 3, wherein said fifth means further comprises: a first decoder means for decoding the first part of said current effective address stored in said first means, so as to select one module from said memory modules; and a second decoder means for decoding the first part of said previous effective address stored in said third means, so as to select one module from said memory modules.
References Cited (Backward Citations)
US4156905A
Cited
US4156290A
Cited
US4296467A
Cited
US4344131A
Cited
US4303993A
Cited
US4323965A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-16 | 1986-11-15 | 1987-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-16 | 1990-11-15 | 1991-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-16 | 1994-11-15 | 1995-05-17 | $7700.00 | Window Closed / Lapsed |