Semiconductor memory device having an improved timing signal generator for the column selection circuit

Claim 2

A memory device comprising an output terminal, means receiving a power voltage, a first drive circuit coupled to said output terminal, said first drive circuit making said output terminal approximately the potential of said power voltage in response to a first timing signal, a first capacitive boost circuit coupled to said output terminal, said first capacitive boost circuit raising the potential at said output terminal, which is approximately at the potential of said power voltage, above said power voltage in response to a second timing signal, said second timing signal being generated after the generation of said first timing signal, and a second capacitive boost circuit coupled to said output terminal, said second capacitive boost circuit operatively raising the potential at said output terminal above said power voltage in response to a third timing signal, said third timing signal being generated only in a write mode and after generation of said second timing signal.

Claim 3

The device according to claim 1, further comprising a second drive circuit coupled to said output terminal for operatively raising the potential at said output terminal above said power voltage after generation of said second timing signal but before the generation of said third timing signal only in the write mode.

Claim 4

The device according to claim 1, in which said second capacitive boost circuit includes a field effect transistor having a current path coupled between said output terminal and a first node, a first capacitor coupled between a second node and a gate of said field effect transistor a second capacitor coupled between said first node and said second node, and means for applying said third timing signal to said second node.

Claim 5

A semiconductor memory device comprising a plurality of word lines, a plurality of digit lines, a plurality of memory cells coupled to said word lines and said digit lines, at least one data bus line, a plurality of transfer gate field effect transistors coupled between said digit lines at said at least one data bus line, a row decoder coupled to said word lines for slecting one of said word lines, and a column decoder coupled to gates of said transfer gate field effect transistors for making a part of said transfer gate field effect transistors conductive, said column decoder including a logic gate receiving addess information, a source-follower transistor, means for connecting a source of said source follower transistor to a gate or gates of the part of said transfer gate field effect transistor, a first boost circuit for operatively generating a first boosted voltage above a power voltage at its output end, a second boost circuit for operatively generated a second voltage above said power voltage after the generation of said first boosted voltage in a write mode, means for applying said first boosted voltage to a drain of said source-follower transistor and means for applying said second boosted voltage to the drain of said source-follower transistor.

Claim 6

A semiconductor memory device comprising a plurality of word lines, a plurality of digit lines, a plurality of memory cells coupled to said word lines and said digit lines, at least one data bus line, a plurality of transfer gate field effect transistors coupled between said digit lines at said at least one data bus line, a row decoder coupled to said word lines for slecting one of said word lines, and a column decoder coupled to gates of said transfer gate field effect transistors for making a part of said transfer gate field effect transistors conductive, said column decoder including a logic gate receiving addess information, a source-follower transistor, means for connecting a source of said source follower transistor to a gate or gates of the part of said transfer gate field effect transistor, a first boost circuit for operatively generating a first boosted voltage above a power voltage at its output end, a second boost circuit for operatively generated a second voltage above said power voltage after the generation of said first boosted voltage in a write mode, means for applying said first boosted voltage to a drain of said source-follower transistor and means for applying said second boosted voltage to the drain of said source-follower transistor.