Semiconductor memory device with voltage bootstrap

Claim 2

A semiconductor memory device having a power source and a plurality of input lines, comprising: a memory cell array having a plurality of memory cells; selection lines for selecting the memory cells in said memory cell array; a selection circuit means for selectively driving said selection lines; at least first and second voltage bootstrap circuits for supplying said selection circuit means with an increased voltage; and control means for controlling said first and second voltage bootstrap circuits to operate alternately in accordance with input signals supplied via said plurality of input lines.

Claim 3

A semiconductor memory device having a power source and a plurality of input lines, comprising: a memory cell array having a plurality of dynamic memory cells for performing write and read operations, said cells requiring a refresh operation; selection lines for selecting the memory cells in said memory cell array; a selection circuit means for selectively driving said selection lines; at least first and second voltage bootstrap circuits for supplying said selection circuit means with an increased voltage; and control means for operating said first voltage bootstrap circuit during said data write and read operations of said memory cell, and operating said second voltage bootstrap circuit during said refreshing of said memory cells, in accordance with input signals supplied via said plurality of input lines.

Claim 4

A semiconductor memory device having a power source and a plurality of input lines, comprising: a memory cell array having a plurality of dynamic memory cells for performing write and read operations, said cells requiring a refresh operation; selection lines for selecting the memory cells in said memory cell array; a selection circuit means for selectively driving said selection lines; at least first and second voltage bootstrap circuits for supplying said selection circuit means with an increased voltage; and control means for operating said first voltage bootstrap circuit during said data write and read operations of said memory cell, and operating said second voltage bootstrap circuit during said refreshing of said memory cells, in accordance with input signals supplied via said plurality of input lines.

Claim 5

A device according to claim 1, wherein said control means includes means for operating said first voltage bootstrap circuit during a first operation period and operating said second voltage bootstrap circuit during a second operation period where lengths of said operation periods are independent of one another.

Claim 6

A device according to claim 2, wherein said first voltage bootstrap circuit includes a first capacitor for supplying said increased voltage, and said second voltage bootstrap circuit includes a second capacitor for supplying said increased voltage, the capacitance of said second capacitor being greater than the capacitance of said first capacitor.

Claim 7

A device according to claim 1, wherein each of said voltage bootstrap circuits comprises: a first inverter for receiving one of said input signals via one of said input lines and having an output; a first capacitor having a first and a second end, said first end connected to said output of said first inverter; a first node connected to said second end of said first capacitor; a load transistor connected to said first node and said power source; a second inverter having an input connected to said output of said first inverter and having an output; a second capacitor having a first and a second end, said first end connected to said output of said second inverter; a second node, connected to said second end of said second capacitor, for providing a potential corresponding to said increased voltage; and a transistor having a current path, connected to said second node, said power source, and a control gate connected to said first node.

Claim 8

A device according to claim 2, wherein each of said voltage bootstrap circuit comprises: a first inverter for receiving one of said input signals via one of said input lines and having an output; a first capacitor having a first and a second end, said first end connected to said output of said first inverter; a first node connected to said second end of said first capacitor; a load transistor connected to said first node and said power source; a second inverter having an input connected to the output of said first inverter and having an output; a second capacitor having an first and a second end, said first end connected to said output of said second inverter; a second node, connected to said second end of said second capacitor, for providing a potential corresponding to said increased voltage, and a transistor having a current path connected to said second node, said power source, and a control gate connected to said first node.

Claim 9

A device according to claim 5, wherein said input signal of said second voltage bootstrap circuit is also supplied to said first node of said first voltage bootstrap circuit, via a capacitor.

Claim 10

A device according to claim 6, wherein said input signal of said second voltage bootstrap circuit is also supplied to said first node of said first voltage bootstrap circuit, via a capacitor.

Claim 11

A device according to claim 5, wherein said second capacitor included in said second voltage bootstrap circuit is charged while said first voltage bootstrap circuit supplies the increased voltage to said selection circuit, and said second capacitor included in said first voltage bootstrap circuit is charged while said second voltage bootstrap circuit supplies the increased voltage to said selection circuit.

Claim 12

A device according to claim 6, wherein said second capacitor included in said second voltage bootstrap circuit is charged while said first voltage bootstrap circuit supplies the increased voltage to said selection circuit, and said second capacitor included in said first voltage bootstrap circuit is charged while said second voltage bootstrap circuit supplies the increased voltage to said selection circuit.

Claim 13

A device according to claim 6, wherein a capacitance of said second capacitor included in said second voltage bootstrap circuit is larger than a capacitance of the second capacitor included in said first voltage bootstrap circuit.

Claim 14

A semiconductor memory device having a power source and a plurality of input lines, comprising: a memory cell array having a plurality of dynamic memory cells which require refreshing and are capable of data write and read operations; selection lines for selecting the memory cells in said memory cell array; selection circuit means for selectively driving said selection lines; a first voltage bootstrap circuit, responsive to a first input signal on said input lines, for supplying said selection circuit means with a first increased voltage during a first operation period to perform data read and write operations of said memory cells; and a second voltage bootstrap circuit, responsive to a second input signal on said input lines, for supplying said selection circuit means with a second increased voltage during a second operation period independent of said first operation period to refesh said memory cells.

Claim 15

A semiconductor memory device having a power source and a plurality of input lines, comprising: a memory cell array having a plurality of dynamic memory cells which require refreshing and are capable of data write and read operations; selection lines for selecting the memory cells in said memory cell array; selection circuit means for selectively driving said selection lines; a first voltage bootstrap circuit, responsive to a first input signal on said input lines, for supplying said selection circuit means with a first increased voltage during a first operation period to perform data read and write operations of said memory cells; and a second voltage bootstrap circuit, responsive to a second input signal on said input lines, for supplying said selection circuit means with a second increased voltage during a second operation period independent of said first operation period to refesh said memory cells.

Claim 16

A device according to claim 12, wherein each of said first and second voltage bootstrap circuits comprises: a first inverter for receiving one of said input signals via one of said input lines and having an output; a first capacitor having a first and a second end, said first end connected to said output of said first inverter; a first node connected to said second end of said first capacitor; a load transistor connected to first node and said power source; a second inverter having an input connected to said output of said first inverter and having an output; a second capacitor having a first and a second end, said first end connected to said output of said second inverter; a second node, connected to said second end of said second capacitor, for providing a potential corresponding to said increased voltage; and a transistor having a current path connected to said second node, said power source, and a control gate connected to said first node.

Claim 17

A device according to claim 13, wherein said input signal of said second voltage bootstrap circuit is also supplied to said first node of said first voltage bootstrap circuit, via a capacitor.

Claim 18

A device according to claim 13, wherein said second capacitor included in said second voltage bootstrap circuit is charged while said first voltage bootstrap circuit supplies the increased voltage to said selection circuit, and said second capacitor included in said first voltage bootstrap circuit is charged while said second voltage bootstrap circuit suppplies the increased voltage to said selection circuit means.

Claim 19

A device according to claim 13, wherein a capacitance of said second capacitor included in said second voltage bootstrap circuit is larger than a capacitance of said second capacitor included in said first voltage bootstrap circuit.

Claim 20

A device according to claim 12, wherein said control means includes means for operating said first voltage bootstrap circuit during a first operation period and operating said second voltage bootstrap circuit during a second operation period where lengths of said operation periods are independent of one another.

Claim 21

A device according to claim 12, wherein said first voltage bootstrap circuit includes a first capacitor for supplying said increased voltage, and said second voltage bootstrap circuit includes a second capacitor for supplying said increased voltage, the capacitance of said second capacitor being greater than the capacitance of said first capacitor.