Semiconductor memory device having a voltage push-up circuit

Claim 2

A semiconductor memory device comprising: (A) a plurality of charge storage type memory cells; (B) a plurality of word lines connected to said plurality of charge storage type memory cells to selectively activate at least one of said plurality of charge storage type memory cells; (C) at least one bit line connected to said plurality of charge storage type memory cells to transfer memory data; (D) sense amplifying means for detecting the memory data on said at least one bit line; and (E) voltage push-up means connected to said at least one bit line for setting a potential on said at least one bit line to an end potential level over a power supply voltage level to increase a charge stored in any of said plurality of charge storage type memory cells said voltage push-up means including (a) a first MOS transistor with a current path connected at one end to said at least one bit line and connected at another end to receive a voltage equal to the power supply voltage level, said first MOS transistor being operative to set said at least one bit line to a first potential level substantially equal to said power supply voltage level at times when said first MOS transistor is conductive, (b) a capacitor connected at one end to receive a first signal applied after the memory data having a predetermined logic level is detected by said sense amplifying means, said first signal having a potential level substantially equal to said power supply voltage level, said capacitor connected at another end to render said first MOS transistor conductive upon application of said first signal, (c) push-up control clock generating circuit means for generating a second potential level higher than said end potential level, and (d) a second MOS transistor with a current path connected at one end to said another end of said capacitor and to a gate of said first MOS transistor and at another end to said at least one bit line and with a gate connected to, and rendered conductive in response to said second potential level for setting the potential on said at least one bit line to said end potential level at times when said first MOS transistor and said second MOS transistor are both conductive at the same time.

Claim 3

A semiconductor memory device according to claim 1, wherein each of said plurality of charge storage type memory cells is formed of a MOS transistor whose gate is connected to a corresponding one of said word lines and a depletion type MOS capacitor connected to said bit line through said MOS transistor.

Claim 4

A semiconductor memory device comprising: (A) a plurality of charge storage type memory cells; (B) a plurality of word lines connected to said plurality of charge storage type memory cells to selectively activate at least one of said plurality of charge storage type memory cells; (C) at least one bit line connected to said plurality of charge storage type memory cells to transfer memory data; (D) sense amplifying means for detecting the memory data on said at least one bit line; and (E) voltage push-up means connected to said at least one bit line for setting a potential on said at least one bit line to an end potential level over a power supply voltage level, to increase a charge stored in any of said plurality of charge storage type memory cells, said at least one bit line being kept at a reference potential level at times when said plurality of charge storage type memory cells are inactive, said voltage push-up means including (a) a first MOS transistor with a current path connected at one end to said at least one bit line and connected at another end to receive a voltage equal to the power supply voltage level, said first MOS transistor being operative to set said at least one bit line to a first potential level substantially equal to said power supply voltage level at times when said first MOS transistor is conductive, (b) a capacitor connected at one end to receive a first signal applied after the memory data having a predetermined logic level is detected by said sense amplifying means, said first signal having a potential level substantially equal to said power supply voltage level, said capacitor connected at another end to render said first MOS transistor conductive upon application of said first signal, (c) push-up control clock generating circuit means for generating a second potential level higher than said end potential level, (d) a second MOS transistor with a current path connected at one end to said another end of said capacitor and to a gate of said first MOS transistor and at another end to said at least one bit line and with a gate connected to, and rendered conductive in response to said second potential level for setting the potential on said at least one bit line to said end potential level at times when said first MOS transistor and said second MOS transistor are both conductive at the same time, and (e) switching means, connected at one end to the connection point between said capacitor and second MOS transistor and connected at another end to receive a voltage equal to said reference potential level, for setting a potential on said connection point at the reference potential level while the said at least one bit line is at the reference potential level.

Claim 5

A semiconductor memory device comprising: (A) a plurality of charge storage type memory cells; (B) a plurality of word lines connected to said plurality of charge storage type memory cells to selectively activate at least one of said plurality of charge storage type memory cells; (C) at least one bit line connected to said plurality of charge storage type memory cells to transfer memory data; (D) sense amplifying means for detecting the memory data on said at least one bit line; and (E) voltage push-up means connected to said at least one bit line for setting a potential on said at least one bit line to an end potential level over a power supply voltage level, to increase a charge stored in any of said plurality of charge storage type memory cells, said at least one bit line being kept at a reference potential level at times when said plurality of charge storage type memory cells are inactive, said voltage push-up means including (a) a first MOS transistor with a current path connected at one end to said at least one bit line and connected at another end to receive a voltage equal to the power supply voltage level, said first MOS transistor being operative to set said at least one bit line to a first potential level substantially equal to said power supply voltage level at times when said first MOS transistor is conductive, (b) a capacitor connected at one end to receive a first signal applied after the memory data having a predetermined logic level is detected by said sense amplifying means, said first signal having a potential level substantially equal to said power supply voltage level, said capacitor connected at another end to render said first MOS transistor conductive upon application of said first signal, (c) push-up control clock generating circuit means for generating a second potential level higher than said end potential level, (d) a second MOS transistor with a current path connected at one end to said another end of said capacitor and to a gate of said first MOS transistor and at another end to said at least one bit line and with a gate connected to, and rendered conductive in response to said second potential level for setting the potential on said at least one bit line to said end potential level at times when said first MOS transistor and said second MOS transistor are both conductive at the same time, and (e) switching means, connected at one end to the connection point between said capacitor and second MOS transistor and connected at another end to receive a voltage equal to said reference potential level, for setting a potential on said connection point at the reference potential level while the said at least one bit line is at the reference potential level.

Claim 6

A semiconductor memory device comprising: (A) a plurality of charge storage type memory cells; (B) a plurality of word lines connected to said plurality of charge storage type memory cells to selectively activate at least one of said plurality of charge storage type memory cells; (C) at least one bit line connected to said plurality of charge storage type memory cells to transfer memory data; (D) sense amplifying means for detecting the memory data on said at least one bit line; and (E) voltage push-up means connected to said at least one bit line for setting a potential on said at least one bit line to an end potential level over a power supply voltage level to increase a charge stored in any of said plurality of charge storage type memory cells, said at least one bit line being kept at a reference potential level at times when said plurality of charge storage type memory cells are inactive, said voltage push-up means including (a) a first MOS transistor with a current path connected at one end to said at least one bit line and connected at another end to receive a voltage equal to the power supply voltage level, said first MOS transistor being operative to set said at least one bit line to a first potential level substantially equal to said power supply voltage level at times when said first MOS transistor is conductive, (b) a capacitor connected at one end to receive a first signal applied after the memory data having a predetermined logic level is detected by said sense amplifying means, said first signal having a potential level substantially equal to said power supply voltage level, said capacitor connected at another end to render said first MOS transistor conductive upon application of said first signal, (c) push-up control clock generating circuit means for generating a second potential level higher than said end potential level, (d) a second MOS transistor with a current path connected at one end to said another end of said capacitor and to a gate of said first MOS transistor and at another end to said at least one bit line and with a gate connected to, and rendered conductive in response to said second potential level for setting the potential on said at least one bit line to said end potential level at times when said first MOS transistor and said second MOS transistor are both conductive at the same time, and (e) a third MOS transistor, connected at one end to the connection point between said capacitor and said second MOS transistor and connected at another end to receive a voltage equal to said reference potential level, for setting a potential on said connection point at the reference potential level while the said at least one bit line is kept at the reference potential level.

Claim 7

A semiconductor memory device comprising: (A) a plurality of charge storage type memory cells; (B) a plurality of word lines connected to said plurality of charge storage type memory cells to selectively activate at least one of said plurality of charge storage type memory cells; (C) at least one bit line connected to said plurality of charge storage type memory cells to transfer memory data; (D) sense amplifying means for detecting the memory data on said at least one bit line; and (E) voltage push-up means connected to said at least one bit line for setting a potential on said at least one bit line to an end potential level over a power supply voltage level to increase a charge stored in any of said plurality of charge storage type memory cells, said at least one bit line being kept at a reference potential level at times when said plurality of charge storage type memory cells are inactive, said voltage push-up means including (a) a first MOS transistor with a current path connected at one end to said at least one bit line and connected at another end to receive a voltage equal to the power supply voltage level, said first MOS transistor being operative to set said at least one bit line to a first potential level substantially equal to said power supply voltage level at times when said first MOS transistor is conductive, (b) a capacitor connected at one end to receive a first signal applied after the memory data having a predetermined logic level is detected by said sense amplifying means, said first signal having a potential level substantially equal to said power supply voltage level, said capacitor connected at another end to render said first MOS transistor conductive upon application of said first signal, (c) push-up control clock generating circuit means for generating a second potential level higher than said end potential level, (d) a second MOS transistor with a current path connected at one end to said another end of said capacitor and to a gate of said first MOS transistor and at another end to said at least one bit line and with a gate connected to, and rendered conductive in response to said second potential level for setting the potential on said at least one bit line to said end potential level at times when said first MOS transistor and said second MOS transistor are both conductive at the same time, and (e) a third MOS transistor, connected at one end to the connection point between said capacitor and said second MOS transistor and connected at another end to receive a voltage equal to said reference potential level, for setting a potential on said connection point at the reference potential level while the said at least one bit line is kept at the reference potential level.