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US4871688A
Expired / Lapsed
US
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Sequence of etching polysilicon in semiconductor memory devices
Assignee: Micron Technology Inc
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Filing: 1988-05-02
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Granted: 1989-10-03
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Expires: 2008-05-02
Abstract
Abstract A semiconductor memory device such as a dymanic random access memory (DRAM) is formed by first forming a burried contact in a silicon wafer and patterning a series of transistors. After the transistors are patterned, oxide layers are applied and the transistors are etched. Cell bottom plates are then formed and electrical connections between the transistors and a periphery are established. The establishment of the transistors are to forming the cell bottom plates and its more efficient manufacture of the DRAM devices and increases manufacturing yield.
Inventors
- 👤 Tyler A. Lowrey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:06
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/30; H10D; H10D1/00; H10D1/01; H10D1/045; H10D1/047
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
221 words
A method of forming DRAM semiconductor circuit devices which include, as a part of each device, a plurality of memory cells and active circuit elements to control signals, the cells and active circuit elements forming a repeating pattern on the device, the method comprising: (a) preparing a silicon substrate; (b) defining active and isolation regions of the substrate by oxidizing the substrate in a pattern, (c) forming an insulation film on a surface of the substrate, said step of forming the insulating film including the formation of gate dielectric in the active regions; (d) removing a portion of the insulating film from said substrate surface to define buried contact regions; (e) forming a polysilicon film, as a first polysilicon layer, over said insulating film and on the portion of said substrate form which the insulating film was removed; (f) introducing impurities into the first polysilicon layer so as to form buried contacts at predetermined portions of the substrate; (g) substantially etching said first polysilicon layer to define a pattern of transistor gates and bit lines from polysilicon connected to said buried contacts; (h) forming a capacitor dielectric layer over the substrate; (i) depositing a second layer of polysilicon over the capacitor dielectric layer; and (j) isotropically etching said second layer of polysilicon, thereby forming capacitors plates over the capacitor dielectric layer.
Claim 2
Independent Claim
221 words
A method of forming DRAM semiconductor circuit devices which include, as a part of each device, a plurality of memory cells and active circuit elements to control signals, the cells and active circuit elements forming a repeating pattern on the device, the method comprising: (a) preparing a silicon substrate; (b) defining active and isolation regions of the substrate by oxidizing the substrate in a pattern, (c) forming an insulation film on a surface of the substrate, said step of forming the insulating film including the formation of gate dielectric in the active regions; (d) removing a portion of the insulating film from said substrate surface to define buried contact regions; (e) forming a polysilicon film, as a first polysilicon layer, over said insulating film and on the portion of said substrate form which the insulating film was removed; (f) introducing impurities into the first polysilicon layer so as to form buried contacts at predetermined portions of the substrate; (g) substantially etching said first polysilicon layer to define a pattern of transistor gates and bit lines from polysilicon connected to said buried contacts; (h) forming a capacitor dielectric layer over the substrate; (i) depositing a second layer of polysilicon over the capacitor dielectric layer; and (j) isotropically etching said second layer of polysilicon, thereby forming capacitors plates over the capacitor dielectric layer.
Claim 3
Dependent Claim
18 words
Method as described in claim 1, further comprising: doping the substrate in the region of the buried contact.
Claim 4
Dependent Claim
15 words
Method as described in claim 2, further comprising: the wafer being provided as P-type material.
Claim 5
Dependent Claim
20 words
Method as described in claim 1, further comprising: the step of forming a capacitor dielectric layer by oxidizing the substrate.
Claim 6
Dependent Claim
22 words
Method as described in claim 1, further comprising: the deposition of said second layer of polysilicon occurring after said anisotropic etch step.
Claim 7
Dependent Claim
29 words
Method as described in claim 1, further comprising: applying a contact pattern consisting of contacts to the wafer subsequent to the isotropically etching of said second layer of polysilicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-02 | 1993-04-03 | 1993-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-02 | 1997-04-03 | 1997-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-02 | 2001-04-03 | 2001-10-03 | $7700.00 | Window Closed / Lapsed |