US4482908A
Expired / Lapsed
US
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High capacity memory cell having a charge transfer channel covered by a stepped insulating layer
Assignee: Samsung Electronics Co Ltd
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Filing: 1984-01-31
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Granted: 1984-11-13
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Expires: 2004-01-31
Abstract
Abstract The disclosed memory cell is comprised of a charge storage region and an adjacent charge transfer channel. A deep dopant layer extends throughout the charge storage region, and a shallow dopant layer extends throughout the charge storage region plus part-way through the charge transfer channel. Overlying the charge storage region is a first conductor that is completely covered by a thick insulating layer. This thick insulating layer also extends into the charge transfer channel part-way over the shallow dopant layer. A thin insulating layer covers the remaining portion of the channel. Lying on this thin insulating layer and extending onto the thick insulating layer is a second conductor. Parasitic capacitance and catastrophic shorts between the two conductors are minimized by the thick insulating layer; charge storage capacity of the storage region is maximized by the two dopant layers lying therein; and cell length is minimized by the thick insulating layer and underlying shallow dopant layer in the charge transfer channel.
Inventors
- 👤 Donald L. Henderson, Sr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 01:46
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/30
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
255 words
An improved memory cell of the type which includes a semiconductor substrate having a major surface, a charge storage region and an adjacent charge transfer channel in said substrate near said surface, an insulating layer on said surface over said charge storage regions, a first conductor on said insulating layer over said charge storage region, wherein the improvement comprises: a deep layer of dopant atoms of a first conductivity type throughout said charge storage region; a shallow layer of dopant atoms of a second conductively type opposite to said first conductivity type throughout said charge storage region and extending therefrom to partway through an adjacent portion of said charge transfer channel; insulating material over said channel and said first conductor having a flat surface in contact with said substrate throughout said channel and being relatively thin over the part of said channel through which said shallow layer of dopant atoms does not extend plus an adjacent portion thereof over said shallow layer followed by two successive stepped increases in thickness through the remainder of said channel over said shallow layer; a second conductor having a stepped surface in face-to-face contact with said stepped insulating material over said charge transfer channel; the distance along said channel from the second conductor at the point where the first stepped increase in thickness in said insulating material begins to said first conductor being less than the length and width of all other components in said cell; and said distance having a dimensional variation of only one mask alignment tolerance.
Claim 2
Dependent Claim
255 words
An improved memory cell of the type which includes a semiconductor substrate having a major surface, a charge storage region and an adjacent charge transfer channel in said substrate near said surface, an insulating layer on said surface over said charge storage regions, a first conductor on said insulating layer over said charge storage region, wherein the improvement comprises: a deep layer of dopant atoms of a first conductivity type throughout said charge storage region; a shallow layer of dopant atoms of a second conductively type opposite to said first conductivity type throughout said charge storage region and extending therefrom to partway through an adjacent portion of said charge transfer channel; insulating material over said channel and said first conductor having a flat surface in contact with said substrate throughout said channel and being relatively thin over the part of said channel through which said shallow layer of dopant atoms does not extend plus an adjacent portion thereof over said shallow layer followed by two successive stepped increases in thickness through the remainder of said channel over said shallow layer; a second conductor having a stepped surface in face-to-face contact with said stepped insulating material over said charge transfer channel; the distance along said channel from the second conductor at the point where the first stepped increase in thickness in said insulating material begins to said first conductor being less than the length and width of all other components in said cell; and said distance having a dimensional variation of only one mask alignment tolerance.
Claim 3
Dependent Claim
42 words
A memory cell according to claim 1 wherein the distance along said channel from said second conductor at the point where the first stepped increase in thickness in said insulating material begins to said first conductor is no more than 1.5 microns.
Claim 4
Dependent Claim
17 words
A memory cell according to claim 2 wherein said dimensional variation is no more than ±0.5 microns.
Claim 5
Dependent Claim
45 words
A memory cell according to claim 3 wherein the thickness of said insulating material between said two successive steps is at least three times thicker than said insulating material over the portion of said channel where said shallow layer of dopant atoms does not extend.
Claim 6
Dependent Claim
52 words
A memory cell according to claim 4 wherein the thickness of said insulating material between said two successive steps is more than 3,000 Å and the thickness of said insulating material over the portion of said channel where said shallow layer of dopant atoms does not extend is less than 500 Å.
Claim 7
Dependent Claim
23 words
A memory cell according to claim 5 wherein said first type dopant atoms are P-type and said second type dopant atoms are N-type.
Claim 8
Dependent Claim
23 words
A memory cell according to claim 5 wherein said first type dopant atoms are N-type and said second type dopant atoms are P-type.
Claim 9
Dependent Claim
17 words
A memory cell according to claim 1 wherein said dimensional variation is no more than ±0.5 microns.
Claim 10
Dependent Claim
45 words
A memory cell according to claim 1 wherein the thickness of said insulating material between said two successive steps is at least three times thicker than said insulating material over the portion of said channel where said shallow layer of dopant atoms does not extend.
Claim 11
Dependent Claim
52 words
A memory cell according to claim 1 wherein the thickness of said insulating material between said two successive steps is more than 3,000 Å and the thickness of said insulating material over the portion of said channel where said shallow layer of dopant atom does not extend is less than 500 Å.
Claim 12
Dependent Claim
23 words
A memory cell according to claim 1 wherein said first type dopant atoms are P-type and said second type dopant atoms are N-type.
Claim 13
Dependent Claim
23 words
A memory cell according to claim 1 wherein said first type dopant atoms are N-type and said second type dopant atoms are P-type.
Claim 14
Dependent Claim
260 words
An improved memory cell of the type which includes a semiconductor substrate having a major surface, a charge storage region and an adjacent charge transfer channel in said substrate near said surface, an insulating layer on said surface over said charge storage region, a first conductor on said insulating layer over said charge storage region, wherein the improvement comprises: a deep layer of dopant atoms of a first conductivity type throughout said charge storage region; a shallow layer of dopant atoms of a second conductivity type opposite to said first conductivity type throughout said charge storage and extending therefrom to partway through an adjacent portion of said charge transfer channel; insulating material over said channel and said first conductor having a flat surface in contact with said substrate throughout said channel and being relatively thin over the part of said channel through which said shallow layer of dopant atoms does not extend plus an adjacent portion thereof over said shallow layer followed by two successive stepped increases in thickness through the remainder of said channel over said shallow layer; a second conductor having a stepped surface in face-to-face contact with said stepped insulating material over said charge transfer channel; at least one of the above recited cell components having a dimension which is the smallest than can be defined by a single photolithographic mask; and the distance from the first stepped increase in thickness in said insulating material to said first conductor being substantially smaller than that smallest dimension yet having a dimensional variation of only one mask alignment tolerance.
Claim 15
Dependent Claim
260 words
An improved memory cell of the type which includes a semiconductor substrate having a major surface, a charge storage region and an adjacent charge transfer channel in said substrate near said surface, an insulating layer on said surface over said charge storage region, a first conductor on said insulating layer over said charge storage region, wherein the improvement comprises: a deep layer of dopant atoms of a first conductivity type throughout said charge storage region; a shallow layer of dopant atoms of a second conductivity type opposite to said first conductivity type throughout said charge storage and extending therefrom to partway through an adjacent portion of said charge transfer channel; insulating material over said channel and said first conductor having a flat surface in contact with said substrate throughout said channel and being relatively thin over the part of said channel through which said shallow layer of dopant atoms does not extend plus an adjacent portion thereof over said shallow layer followed by two successive stepped increases in thickness through the remainder of said channel over said shallow layer; a second conductor having a stepped surface in face-to-face contact with said stepped insulating material over said charge transfer channel; at least one of the above recited cell components having a dimension which is the smallest than can be defined by a single photolithographic mask; and the distance from the first stepped increase in thickness in said insulating material to said first conductor being substantially smaller than that smallest dimension yet having a dimensional variation of only one mask alignment tolerance.
Claim 16
Dependent Claim
42 words
A memory cell according to claim 13 wherein the distance along said channel from said second conductor at the point where the first stepped increase in thickness in said insulating material begins to said first conductor is no more than 1.5 microns.
Claim 17
Dependent Claim
17 words
A memory cell according to claim 13 wherein said dimensional variation is no more than ±0.5 microns.
Claim 18
Dependent Claim
45 words
A memory cell according to claim 13 wherein the thickness of said insulating material between said two successive steps is at least three times thicker than said insulating material over the portion of said channel where said shallow layer of dopant atoms does not extend.
Claim 19
Dependent Claim
52 words
A memory cell according to claim 13 wherein the thickness of said insulating material between said two successive steps is more than 3,000 Å and the thickness of said insulating material over the portion of said channel where said shallow layer of dopant atoms does not extend is less than 500 Å.
Claim 20
Dependent Claim
23 words
A memory cell according to claim 13 wherein said first type dopant atoms are P-type and said second type dopant atoms are N-type.
Claim 21
Dependent Claim
23 words
A memory cell according to claim 13 wherein said first type dopant atoms are N-type and said second type dopant atoms are P-type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-13 | 1988-05-14 | 1988-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-13 | 1992-05-14 | 1992-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-13 | 1996-05-14 | 1996-11-13 | $7700.00 | Window Closed / Lapsed |