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US4558343A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device having a high resistivity layer in direct contact with a polycrystalline silicon layer of high impurity concentration

Assignee: Toshiba Corp
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Filing: 1984-10-26
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Granted: 1985-12-10
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Expires: 2004-10-26
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Abstract

Abstract This invention provides a semiconductor device, which has a high impurity concentration diffusion region such as a drain diffusion region and a resistor comprising a polycrystalline silicon layer (which may be a load of a driver MOS transistor), and in which part of the resistor is in direct contact with the high impurity concentration diffusion region. This invention also provides a method of manufacturing a semiconductor device, which comprises the steps of forming a gate electrode and drain and source diffusion regions along the principal surface of a semiconductor substrate, then forming a polycrystalline silicon resistor layer of a comparatively low impurity concentration such that it is in direct contact with a diffusion region, and subsequently causing impurity diffusion from the diffusion region through thermal treatment to obtain ohmic contact between the diffusion region and resistor layer.

Inventors

  • 👤 Syoji Ariizumi
  • 👤 Yasushi Fukatsu
  • 👤 Fujio Masuoka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 08:43
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 241 words
In a semiconductor device having a first MOS transistor and a second MOS transistor separated by a field oxide layer from the first MOS transistor, a structure comprising: a semiconductor substrate of one conductivity type; a high impurity concentration diffusion region formed in the surface of said semiconductor substrate and doped with an impurity of the opposite conductivity type to that of said substrate, said region being the drain diffusion region of said first MOS transistor; a first polycrystalline silicon layer doped with an impurity of said opposite conductivity type and extending over said field oxide layer, and one end of which is connected with a portion of said high impurity concentration diffusion region; an oxide layer extending over a portion of said first polycrystalline silicon layer; a resistor comprising a second polycrystalline silicon layer disposed over either one of the gate electrodes of the first and second MOS transistors, one end of said resistor being in direct contact with said first polycrystalline silicon layer through an opening provided over the field oxide layer through said oxide layer, and impurities being thermally diffused from said first polycrystalline silicon layer into that portion of said second polycrystalline silicon layer which is in contact with said first polycrystalline silicon layer, thereby electrically connecting both the first and second polycrystalline silicon layers; and another end portion of said first polycrystalline silicon layer constituting a gate electrode of the gate of said second MOS transistor.
Claim 2
Dependent Claim 241 words
In a semiconductor device having a first MOS transistor and a second MOS transistor separated by a field oxide layer from the first MOS transistor, a structure comprising: a semiconductor substrate of one conductivity type; a high impurity concentration diffusion region formed in the surface of said semiconductor substrate and doped with an impurity of the opposite conductivity type to that of said substrate, said region being the drain diffusion region of said first MOS transistor; a first polycrystalline silicon layer doped with an impurity of said opposite conductivity type and extending over said field oxide layer, and one end of which is connected with a portion of said high impurity concentration diffusion region; an oxide layer extending over a portion of said first polycrystalline silicon layer; a resistor comprising a second polycrystalline silicon layer disposed over either one of the gate electrodes of the first and second MOS transistors, one end of said resistor being in direct contact with said first polycrystalline silicon layer through an opening provided over the field oxide layer through said oxide layer, and impurities being thermally diffused from said first polycrystalline silicon layer into that portion of said second polycrystalline silicon layer which is in contact with said first polycrystalline silicon layer, thereby electrically connecting both the first and second polycrystalline silicon layers; and another end portion of said first polycrystalline silicon layer constituting a gate electrode of the gate of said second MOS transistor.
Claim 3
Dependent Claim 42 words
The semiconductor device according to claim 1, wherein the impurity concentration of said first polycrystalline silicon layer ranges from 10 19 to 10 21 atoms/cm 3 , and wherein the resistivity of said resistor ranges from 10 6 to 10 11 Ω/□.
Claim 4
Dependent Claim 23 words
The semiconductor device according to claim 1, wherein said resistor has a substantially uniform impurity concentration distribution except for said one end thereof.
Claim 5
Dependent Claim 26 words
The semiconductor device according to claim 1, wherein the high impurity concentration layer, said resistor and said high impurity concentration diffusion region constitute an inverter circuit.
Claim 6
Dependent Claim 35 words
The semiconductor device according to claim 1, wherein said high impurity concentration diffusion region is a drain diffusion region of an MOS transistor and said resistor extends over a gate electrode of said MOS transistor.
Claim 7
Dependent Claim 38 words
The semiconductor device according to claim 1, wherein said high impurity concentration diffusion region is a drain diffusion region of an MOS transistor, and together with said resistor and said high impurity concentration layer constitutes an inverter circuit.

References Cited (Backward Citations)

US3519901A Cited
US4146902A Cited
US4110776A Cited
US4209716A Cited
US4270137A Cited
US4246593A Cited
US4322824A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-12-09 1989-06-10 1989-12-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-12-09 1993-06-10 1993-12-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-12-09 1997-06-10 1997-12-10 $7700.00 Window Closed / Lapsed

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