Method of producing a two-dimensional electron gas semiconductor device

Claim 1

A method of producing a semiconductor device which comprises an enhancement-mode transistor and a depletion-mode transistor on a common substrate, has a heterojunction, and utilizes a two-dimensional electron gas, comprising the steps of: forming a semiconductor channel layer, in which the two-dimensional electron gas is generated, on a semi-insulating compound semiconductor substrate; forming an electron supply layer of AlGaAs on said semiconductor channel layer, which layers form the heterojunction; forming a first semiconductor layer of GaAs on said electron supply layer; forming a second semiconductor layer of AlGaAs on said first semiconductor layer; selectively etching a portion of said second semiconductor layer corresponding to a gate region of the enhancement-mode transistor to form a recess in which said first semiconductor layer is exposed; in a common etching method, etching the exposed portion of said first semiconductor layer and a portion of said electron supply layer having a thickness corresponding to the thickness of said second semiconductor layer to form a groove for the gate of the enhancement-mode transistor and simultaneously etching a portion of said second semiconductor layer and a portion of said first semiconductor layer to expose said electron supply layer and to form another groove for the gate electrode of the depletion-mode transistor; and forming said gate electrodes in said grooves, respectively; wherein said etching method is a reactive ion etching method using an etching gas comprising CCl 2 F 2 , which etches rapidly said first semiconductor layer of GaAs and etches slowly said second semiconductor layer and said electron supply layer of AlGaAs.

Claim 2

A method of producing a semiconductor device which comprises an enhancement-mode transistor and a depletion-mode transistor on a common substrate, has a heterojunction, and utilizes a two-dimensional electron gas, comprising the steps of: forming a semiconductor channel layer, in which the two-dimensional electron gas is generated, on a semi-insulating compound semiconductor substrate; forming an electron supply layer of AlGaAs on said semiconductor channel layer, which layers form the heterojunction; forming a first semiconductor layer of GaAs on said electron supply layer; forming a second semiconductor layer of AlGaAs on said first semiconductor layer; selectively etching a portion of said second semiconductor layer corresponding to a gate region of the enhancement-mode transistor to form a recess in which said first semiconductor layer is exposed; in a common etching method, etching the exposed portion of said first semiconductor layer and a portion of said electron supply layer having a thickness corresponding to the thickness of said second semiconductor layer to form a groove for the gate of the enhancement-mode transistor and simultaneously etching a portion of said second semiconductor layer and a portion of said first semiconductor layer to expose said electron supply layer and to form another groove for the gate electrode of the depletion-mode transistor; and forming said gate electrodes in said grooves, respectively; wherein said etching method is a reactive ion etching method using an etching gas comprising CCl 2 F 2 , which etches rapidly said first semiconductor layer of GaAs and etches slowly said second semiconductor layer and said electron supply layer of AlGaAs.

Claim 5

A method according to any one of claims 1, 2 or 3, further comprising the steps, before said formation step of the first semiconductor layer, of: forming a third semiconductor layer, being of the same material as said first semiconductor layer, on said electron-supply layer; and forming a fourth semiconductor layer, being of the same material as said second semiconductor layer and having the same thickness as said second semiconductor layer, on said third semiconductor layer.