Method for fabricating buried channel field effect transistor for microwave and millimeter frequencies utilizing molecular beam epitaxy

Claim 1

A process for fabricating a field effect transistor, comprising the steps of: (a) supplying a semi-insulating crystal wafer having an upper and lower surface, and a right-hand, left-hand and central region on its upper surface, (b) depositing a thin, amorphous, silicon dioxide layer over the upper surface of the device, (c) removing the silicon dioxide layer over the right-hand, left-hand and central regions to expose the surface of the semi-insulating crystal in these regions, (d) depositing by means of molecular beam epitaxy an N+ layer over the upper surface of the device, this deposition forming N+ layers over the exposed crystaline structure in the right-hand, left-hand and central regions and forming a semi-insulating barrier over the amorphous silicon dioxide layer, said barrier surrounding the right-hand, left-hand and central regions, (e) depositing an N layer over the upper surface of the wafer, (g) depositing a semi-insulating layer over the N layer, (h) removing a portion of the semi-insulating layer over the central region to expose the N layer, which forms the gate of the field effect transistor, and (i) removing a portion of the semi-insulating layer and the N layer over the left and right-hand regions to expose the N+ layer, which form the drains of the field effect transistor, and (j) making contact with the N+ layer in the central N+ region, which forms the source for the field effect transistor.