US4814638A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed digital driver with selectable level shifter
Assignee: Grumman Corp
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Filing: 1987-06-08
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Granted: 1989-03-21
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Expires: 2007-06-08
Abstract
Abstract A driver is utilized at the output of a digital word generator for translating a digital word to selectable voltage levels in accordance with a particular unit connected to the output of the driver and undergoing diagnostic testing. The driver has a separate control line for switching the driver to a tri-state mode so that the input of a unit undergoing test may be switched to a high impedance input, thereby permitting tri-state diagnostic testing of a unit undergoing test.
Inventors
- 👤 John M. Weick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 09:16
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017581; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31924; H03K19/01; H03K19/013; H03K19/02; H03K19/08; H03K19/082; H03K19/0823; H03K19/0826
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
173 words
A digital driver for variably translating low level input signals from an automatic test equipment to programmable levels acceptable to a unit undergoing test, the driver having two parallel paths for respectively processing first and second binary bit levels of the input signal, each path comprising: means for shifting the low level input by a fixed amount; a variable voltage potential; switching means connected at a control terminal to an output of the level shifting means for switching the switching means in synchronism with the input signal; means connecting the voltage potential to the switching means for generating a signal with a translated level at an output of the switching means; means connecting an output of the switching means to an input of a unit undergoing test so that the outputs of the switching means for the two parallel paths are connected together thus providing an output binary signal corresponding to and in synchronism with the input signal but wherein the levels of the output binary signal are dependent upon respective voltage potentials.
Claim 2
Dependent Claim
173 words
A digital driver for variably translating low level input signals from an automatic test equipment to programmable levels acceptable to a unit undergoing test, the driver having two parallel paths for respectively processing first and second binary bit levels of the input signal, each path comprising: means for shifting the low level input by a fixed amount; a variable voltage potential; switching means connected at a control terminal to an output of the level shifting means for switching the switching means in synchronism with the input signal; means connecting the voltage potential to the switching means for generating a signal with a translated level at an output of the switching means; means connecting an output of the switching means to an input of a unit undergoing test so that the outputs of the switching means for the two parallel paths are connected together thus providing an output binary signal corresponding to and in synchronism with the input signal but wherein the levels of the output binary signal are dependent upon respective voltage potentials.
Claim 3
Dependent Claim
70 words
The structure set forth in claim 1 together with gating means connected at an output thereof to an input of each level shifting means, the input signal provided at the input of the gating means for passage to the parallel paths; the gating means having a tri-state control input for opening the gating means and producing a high output impedance at the switching means output regardless of the input signal.
Claim 4
Dependent Claim
54 words
The structure set forth in claim 2 together with means associated with each path and connected to the means connecting the voltage potential to the switching means for detecting an overload condition, an output of the detecting means connected to the level shifting means for opening the path until the overload condition is corrected.
Claim 5
Dependent Claim
22 words
The structure set forth in claim 3 together with means connected to the switching means for preventing saturation of the switching means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-20 | 1992-09-19 | 1993-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-20 | 1996-09-19 | 1997-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-20 | 2000-09-19 | 2001-03-21 | $7700.00 | Window Closed / Lapsed |