US3742253A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Three state logic device with applications
Assignee: Unisys Corp
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Filing: 1971-03-15
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Granted: 1973-06-26
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Expires: 1991-03-15
Abstract
Abstract An electronic circuit responsive to three combinations of binary input signals is disclosed. The circuit has two input terminals and two output terminals and is responsive to three combinations of binary input signals with the combination of two binary zeros following two binary ones being forbidden as an input to the circuit. The electronic circuit may advantageously be designed to be used as an RS flip-flop and is useful in the transmission of asynchronous information and may be employed with a transmission gate on the input side which applies a binary one to each input when there is no data to be transferred through the electronic device or when there is inconsistent data from plural sources at the inputs of the device.
Inventors
- 👤 R Kronies
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:05
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239; G06F13/14; G06F13/16; G06F13/18; H; H03; H03K; H03K19/00; H03K19/0002
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
106 words
Method of sequencing binary input signals to an electronic circuit having two input terminals and capable of operating as an RS flip-flop to cause it to operate as an RS flip-flop for a first and a second combination of binary input signals and as a combination logic element for a third combination of binary input signals comprising the steps of applying a binary one to only one input as either a pulse or a continuous level, applying a binary one to both inputs as continuous levels, and permitting only one input to become a binary zero following the application of the binary one to both inputs.
Claim 2
Dependent Claim
106 words
Method of sequencing binary input signals to an electronic circuit having two input terminals and capable of operating as an RS flip-flop to cause it to operate as an RS flip-flop for a first and a second combination of binary input signals and as a combination logic element for a third combination of binary input signals comprising the steps of applying a binary one to only one input as either a pulse or a continuous level, applying a binary one to both inputs as continuous levels, and permitting only one input to become a binary zero following the application of the binary one to both inputs.
Claim 3
Dependent Claim
106 words
Method of sequencing binary input signals to an electronic circuit having two input terminals and designed to function as an RS flip-flop to cause it to operate as an RS flip-flop for a first and a second combination of binary input signals and as a combinational logic element for a third combination of binary input signals comprising the steps of applying a binary one to only one input as either a pulse or a continuous level, applying a binary one to both inputs as continuous levels, and permitting only one input to become a binary zero following the application of the binary one to both inputs.
Claim 4
Dependent Claim
106 words
Method of sequencing binary input signals to an electronic circuit having two input terminals and designed to function as an RS flip-flop to cause it to operate as an RS flip-flop for a first and a second combination of binary input signals and as a combinational logic element for a third combination of binary input signals comprising the steps of applying a binary one to only one input as either a pulse or a continuous level, applying a binary one to both inputs as continuous levels, and permitting only one input to become a binary zero following the application of the binary one to both inputs.
Claim 5
Dependent Claim
292 words
In combination, a plurality of electronic circuits each having at least two input terminals and one output terminal and including a first OR gate having at least a first input terminal and a second input terminal, a first inverter connected to the output of the first OR gate, a second OR gate having at least a first input terminal and a second input terminal, a second inverter connected to the output of the second OR gate, means for coupling the output of the first inverter to the first input terminal of the second OR gate, means for coupling the output of the second inverter to the first input terminal of the first OR gate, means for coupling the output of one of the inverters to the output terminal, means for connecting the second input terminal of the first OR gate to the first input terminal of the electronic circuit, and means for connecting the second input terminal of the second OR gate to the second input terminal of the electronic circuit; means for utilizing the binary outputs of the electronic circuit; a controllable transmission gate connected between the utilization means and the outputs of each electronic circuit; a plurality of inverters; a source having plural outputs of binary coded data each output of the source being directly coupled to on input terminal of an electronic circuit and through an inverter to the other input terminal of the electronic circuit; a source of strobe signals in binary form indicating the presence of binary data to be transferred from the source through the electronic circuits to the utilization means; and means for coupling the output of the strobe source through an inverter and individual isolation means To both input terminals of each electronic circuit.
Claim 6
Dependent Claim
292 words
In combination, a plurality of electronic circuits each having at least two input terminals and one output terminal and including a first OR gate having at least a first input terminal and a second input terminal, a first inverter connected to the output of the first OR gate, a second OR gate having at least a first input terminal and a second input terminal, a second inverter connected to the output of the second OR gate, means for coupling the output of the first inverter to the first input terminal of the second OR gate, means for coupling the output of the second inverter to the first input terminal of the first OR gate, means for coupling the output of one of the inverters to the output terminal, means for connecting the second input terminal of the first OR gate to the first input terminal of the electronic circuit, and means for connecting the second input terminal of the second OR gate to the second input terminal of the electronic circuit; means for utilizing the binary outputs of the electronic circuit; a controllable transmission gate connected between the utilization means and the outputs of each electronic circuit; a plurality of inverters; a source having plural outputs of binary coded data each output of the source being directly coupled to on input terminal of an electronic circuit and through an inverter to the other input terminal of the electronic circuit; a source of strobe signals in binary form indicating the presence of binary data to be transferred from the source through the electronic circuits to the utilization means; and means for coupling the output of the strobe source through an inverter and individual isolation means To both input terminals of each electronic circuit.
Claim 7
Dependent Claim
59 words
The combination in accordance with claim 3 further comprising logic circuit means for detecting the presence of binary data from an individual source at the output of each of the electronic circuits and when such binary data is present at the output of a selected plurality of electronic circuits for transferring the binary data therein to the utilization means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-25 | 1976-12-25 | 1977-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-25 | 1980-12-25 | 1981-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-25 | 1984-12-25 | 1985-06-26 | $7700.00 | Window Closed / Lapsed |