US3575608A
Expired / Lapsed
US
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Circuit for detecting a change in voltage level in either sense
Assignee: RCA Corp
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Filing: 1969-07-29
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Granted: 1971-04-20
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Expires: 1989-07-29
Abstract
Abstract First and second cross-coupled logic gates respectively connected to third and fourth logic gates, with feedback connections from the third to the second and the fourth to the first gate. The input voltage level whose change in value it is desired to sense is applied to the third gate and its complement is applied to the second and fourth gates. When this input voltage changes its value in one sense, an output pulse is produced by the third gate and when it changes its value in the opposite sense, an output pulse is produced by the fourth gate. The logic gates may be NAND or NOR gates.
Inventors
- 👤 Donald John Barth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:29
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1534; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
127 words
A circuit for detecting a change in voltage level in either sense comprising, in combination: first and second cross-coupled logic gates; a third logic gate connected to receive the output of the first logic gate; a fourth logic gate connected to receive the output of the second logic gate; a feedback connection from the output of the third logic gate to the second logic gate; a feedback connection from the output of the fourth logiC gate to the first logic gate; and means for applying the voltage whose level is being sensed and which is indicative of a binary digit of one value to said third logic gate and a complementary voltage level indicative of the binary digit of other value to the second and fourth gates.
Claim 2
Dependent Claim
127 words
A circuit for detecting a change in voltage level in either sense comprising, in combination: first and second cross-coupled logic gates; a third logic gate connected to receive the output of the first logic gate; a fourth logic gate connected to receive the output of the second logic gate; a feedback connection from the output of the third logic gate to the second logic gate; a feedback connection from the output of the fourth logiC gate to the first logic gate; and means for applying the voltage whose level is being sensed and which is indicative of a binary digit of one value to said third logic gate and a complementary voltage level indicative of the binary digit of other value to the second and fourth gates.
Claim 3
Dependent Claim
15 words
In the combination set forth in claim 1 said four gates comprising four NAND gates.
Claim 4
Dependent Claim
15 words
In the combination set forth in claim 1 said four gates comprising four NOR gates.
Claim 5
Dependent Claim
34 words
In the combination set forth in claim 1 a fifth gate coupled to said third and fourth gates for producing an output pulse when either the third or fourth gate produces an output pulse.
References Cited (Backward Citations)
US3458825A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-19 | 1974-10-19 | 1975-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-19 | 1978-10-19 | 1979-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-19 | 1982-10-19 | 1983-04-20 | $7700.00 | Window Closed / Lapsed |