US3671763A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ternary latches
Assignee: International Business Machines Corp
•
Filing: 1971-02-05
•
Granted: 1972-06-20
•
Expires: 1991-02-05
Abstract
Abstract Two latch circuits are disclosed for three-state operation in the ternary mode. The set input may be raised to a 1 or intermediate voltage level thereby providing a 1 level at the output which remains latched at that level after the set input is lowered to the 0 or lowermost level. When the set input is raised to the uppermost or 2 level the output is set at the 2 level and remains latched at that level when the set input is lowered to the 0 level. The circuits are reset to 0 by raising the reset input to the 2 level.
Inventors
- 👤 Gerald A Maley
- 👤 James L Walsh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:47
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/29
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
92 words
A ternary latch circuit comprising a set input, a reset input, and an output, means for latching the output at an intermediate signal level in response to raising of the signal to the set input from a lowermost level to an intermediate level, means for latching the output at an uppermost signal level in response to the application of an uppermost level signal to the set input, and means for resetting the output to a lowermost level signal in response to the application of a raised level signal to the reset input.
Claim 2
Dependent Claim
92 words
A ternary latch circuit comprising a set input, a reset input, and an output, means for latching the output at an intermediate signal level in response to raising of the signal to the set input from a lowermost level to an intermediate level, means for latching the output at an uppermost signal level in response to the application of an uppermost level signal to the set input, and means for resetting the output to a lowermost level signal in response to the application of a raised level signal to the reset input.
Claim 3
Dependent Claim
56 words
A ternary latch circuit as recited in claim 1 and comprising means for maintaining said output signal at said intermediate level after said signal at the set input returns to a lowermost level, and means for maintaining said output signal at said uppermost level after said signal at the set input returns to a lowermost level.
Claim 4
Dependent Claim
87 words
A ternary latch circuit as recited in claim 1 wherein said several means comprise constant current source means providing two units of current, a load resistor, means connecting said output to said load resistor, means for causing one unit of current to flow through said load resistor in response to the application of an intermediate level signal to the set input, and means for bypassing both units of current around said load resistor in response to the application of an uppermost level signal to the set input.
Claim 5
Dependent Claim
58 words
A ternary latch circuit comprising a set input adapted to assume any one of three signal levels, an output adapted to assume any one of three signal levels, and means for latching the output at an intermediate signal level in response to raising of the signal to the set input from a lowermost level to an intermediate level.
Claim 6
Dependent Claim
58 words
A ternary latch circuit comprising a set input adapted to assume any one of three signal levels, an output adapted to assume any one of three signal levels, and means for latching the output at an intermediate signal level in response to raising of the signal to the set input from a lowermost level to an intermediate level.
Claim 7
Dependent Claim
35 words
A ternary latch circuit as recited in claim 4 and comprising means for providing an uppermost level signal at the output in response to the application of an uppermost level signal to the set input.
Claim 8
Dependent Claim
39 words
A ternary latch circuit as recited in claim 4 and comprising a reset input, and means for resetting the output to a lowermost level signal in response to the application of a raised level signal to the reset input.
Claim 9
Dependent Claim
33 words
A ternary latch circuit as recited in claim 4 and comprising means for maintaining said output signal at said intermediate level after said signal at the set input returns to a lowermost level.
Claim 10
Dependent Claim
87 words
A ternary latch circuit comprising a set input adapted to assume any one of three signal levels, an output adapted to assume any one of three signal levels, means for latching the output at an uppermost signal level in response to the application of an uppermost level signal to the set input, means for latching the output at an intermediate level a reset input, and means for resetting the output to a lowermost signal level in response to the application of a signal to the reset input.
Claim 11
Dependent Claim
87 words
A ternary latch circuit comprising a set input adapted to assume any one of three signal levels, an output adapted to assume any one of three signal levels, means for latching the output at an uppermost signal level in response to the application of an uppermost level signal to the set input, means for latching the output at an intermediate level a reset input, and means for resetting the output to a lowermost signal level in response to the application of a signal to the reset input.
Claim 12
Dependent Claim
33 words
A ternary latch circuit as recited in claim 8 and comprising means for maintaining said output signal at said uppermost level after said signal at the set input returns to a lowermost level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-20 | 1975-12-20 | 1976-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-20 | 1979-12-20 | 1980-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-20 | 1983-12-20 | 1984-06-20 | $7700.00 | Window Closed / Lapsed |