Three state output circuit

Claim 2

A three state output circuit comprising: active pull down means coupled to an input node and an output node, for coupling the output node to a first supply voltage in response to an assert signal having a first predetermined voltage level; threshold detection means coupled to the output node, for providing a reset signal in response to the voltage on the output node exceeding a predetermined threshold voltage; latch means coupled to the input node and the threshold detection means, for providing an enable signal in response to said assert signal, and, in the absence of said assert signal, terminating said enable signal in response to said reset signal; gate means coupled to the input node and the latch means, for passing a rescind signal having a second predetermined voltage level in response to the coincidence of said rescind signal and said enable signal; and active pull up means coupled to the gate means and the output node, for coupling the output node to a second supply voltage in response to said rescind signal passed by the gate means.

Claim 3

The circuit of claim 1 wherein the latch means has a set input coupled to the input node, a reset input coupled to the threshold detector, and an output coupled to the gate means.

Claim 4

The circuit of claim 2, wherein the latch means comprises a pair of cross-coupled NOR gates.

Claim 5

The circuit of claim 2 wherein the output of the latch means is dominated by the assert signal coupled to the set input thereof.

Claim 6

The circuit of claim 2 wherein the threshold detector comprises: first means for passively pulling the reset input of the latch means towards the first reference voltage; and second means for actively pulling the reset input of the latch means towards the second reference voltage when the voltage on the output node exceeds the predetermined threshold voltage, the second means being capable of overpowering the first means.

Claim 7

The circuit of claim 5 wherein the first means comprises a depletion type transistor having the gate and source thereof coupled to the first reference voltage, and the drain thereof coupled to the reset input of the latch means; and wherein the second means comprises an enhancement type transistor capable of conducting more current than said depletion transistor and having the source thereof coupled to the reset input of the latch means, the drain thereof coupled to the second reference voltage, and the gate thereof coupled to the output node, the threshold voltage of the enhancement transistor establishing said predetermined threshold voltage.

Claim 8

The circuit of claim 1 wherein the pull down and the pull up devices are enhancement type transistors.

Claim 9

The circuit of claim 1 wherein said gate means comprises a NOR gate.

Claim 10

A three state output circuit comprising: active pull down means responsive to an assert signal having a first predetermined voltage level, for coupling an output node to a first supply voltage in response to said assert signal; threshold detection means responsive to the voltage on said output node, for providing a reset signal in response to the voltage on said output node exceeding a predetermined threshold voltage; latch means responsive to said assert signal and said reset signal, for providing an enable signal in response to said assert signal, and, in the absence of said assert signal, terminating said enable signal in response to said reset signal; gate means responsive to said enable signal and a rescind signal having a second predetermined voltage level; for passing said rescind signal in response to the coincidence of said rescind signal and said enable signal; and active pull up means responsive to said rescind signal passed by said gate means, for coupling said output node to a second supply voltage in response to said rescind signal passed by said gate means.

Claim 11

A three state output circuit comprising: active pull down means responsive to an assert signal having a first predetermined voltage level, for coupling an output node to a first supply voltage in response to said assert signal; threshold detection means responsive to the voltage on said output node, for providing a reset signal in response to the voltage on said output node exceeding a predetermined threshold voltage; latch means responsive to said assert signal and said reset signal, for providing an enable signal in response to said assert signal, and, in the absence of said assert signal, terminating said enable signal in response to said reset signal; gate means responsive to said enable signal and a rescind signal having a second predetermined voltage level; for passing said rescind signal in response to the coincidence of said rescind signal and said enable signal; and active pull up means responsive to said rescind signal passed by said gate means, for coupling said output node to a second supply voltage in response to said rescind signal passed by said gate means.