Abstract A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.
A method for forming a coupled capacitor and transistor comprising the steps of; forming a trench in the surface of a substrate; coating the surfaces of said trench with a first insulating layer; forming a first conductive region by filling the lower portion of said trench with a conductive material; removing the exposed portion of said insulating layer plus an additional portion of said insulating layer between said conductive material and said substrate; filling the crevice formed by said additional portion removal with a conductive material; diffusing dopant atoms from said first conductive region, through said filled crevice, into said substrate to form a source region; forming a drain region in said substrate adjacent the upper portion of said trench, separated from said source region by a channel region; forming a gate insulating layer in the upper portion of said trench; and filling the remainder of said trench with a conductive material which serves as a gate.
Claim 2
Independent Claim
157 words
A method for forming a coupled capacitor and transistor comprising the steps of; forming a trench in the surface of a substrate; coating the surfaces of said trench with a first insulating layer; forming a first conductive region by filling the lower portion of said trench with a conductive material; removing the exposed portion of said insulating layer plus an additional portion of said insulating layer between said conductive material and said substrate; filling the crevice formed by said additional portion removal with a conductive material; diffusing dopant atoms from said first conductive region, through said filled crevice, into said substrate to form a source region; forming a drain region in said substrate adjacent the upper portion of said trench, separated from said source region by a channel region; forming a gate insulating layer in the upper portion of said trench; and filling the remainder of said trench with a conductive material which serves as a gate.
Claim 3
Dependent Claim
11 words
A method according to claim 1 wherein said substrate comprises silicon.
Claim 4
Dependent Claim
14 words
A method according to claim 1 wherein said first insulating layer comprises silicon dioxide.
Claim 5
Dependent Claim
14 words
A method according to claim 1 wherein said gate insulating layer comprises silicon dioxide.
Claim 6
Dependent Claim
13 words
A method according to claim 1 wherein the conductive material used is silicon.