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US4769337A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming selective polysilicon wiring layer to source, drain and emitter regions by implantation through polysilicon layer

Assignee: Toshiba Corp
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Filing: 1987-05-08
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Granted: 1988-09-06
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Expires: 2007-05-08
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Abstract

Abstract A method of manufacturing a semiconductor device, comprises the process of forming first and second well regions, which are of N-type and P-type, respectively, in a silicon body, forming a base layer of P-type in the first well region, forming an emitter layer of N-type in the base layer, forming source and drain layers of N-type in the second well region, forming a polysilicon emitter electrode on the emitter layer, and ion-implanting impurities of N-type into an interface between the emitter layer and the emitter electrode, so as to break down an insulative layer at the interface.

Inventors

  • 👤 Takeo Maeda

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 23:01
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; Y; Y10; Y10S; Y10S148/00; Y10S148/14

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 111 words
A method of manufacturing a semiconductor device, comprising the processes of: forming first and second well regions, which are of first and second conductivity types, respectively, in a semiconductor body; forming a base layer of the second conductivity type in the first well region; forming an emitter layer of the first conductivity type in the base layer; forming source and drain layers of the first conductivity type in the second well region; forming a polysilicon emitter electrode on the emitter layer; and ion-implanting impurities of the first conductivity type into an interface between the emitter layer and the emitter electrode, so as to break down an insulative layer at the interface.
Claim 2
Independent Claim 111 words
A method of manufacturing a semiconductor device, comprising the processes of: forming first and second well regions, which are of first and second conductivity types, respectively, in a semiconductor body; forming a base layer of the second conductivity type in the first well region; forming an emitter layer of the first conductivity type in the base layer; forming source and drain layers of the first conductivity type in the second well region; forming a polysilicon emitter electrode on the emitter layer; and ion-implanting impurities of the first conductivity type into an interface between the emitter layer and the emitter electrode, so as to break down an insulative layer at the interface.
Claim 3
Dependent Claim 68 words
A method of manufacturing a semiconductor device according to claim 1, further comprising the processes of: forming a third well region of the first conductivity type in the semiconductor body such that the third well region is isolated from the first well region by an isolating layer of the second conductivity type; and forming source and drain layers of the second conductivity type in the third well region.
Claim 4
Independent Claim 235 words
A method of manufacturing a semiconductor device, comprising the processes of: forming first and second well regions, which are of first and second conductivity types, respectively, in a semiconductor body; forming a gate insulation film on one side of each of the first and second well regions; forming a base layer of the second conductivity type on one side of the first well region; forming a contact hole in that part of the gate insulation film which is located on the base layer, thereby exposing part of the base layer; forming a polysilicon film on the gate insulation film and on an exposed part of the base layer; forming an emitter layer by introducing impurities of the first conductivity type into the base layer through the polysilicon film located on the exposed part of the base layer; ion-implanting impurities of the first conductivity type into an interface between the polysilicon film and the emitter layer, thereby breaking down an insulating film at the interface; removing a composite film, which includes the gate insulating film and the polysilicon film located on the second well region, such that the composite film remains in part on the second well region; ion-implanting impurities of the first conductivity type into the second well region, using the remaining composite film as a mask, thereby forming source and drain layers; and covering one side of the well regions with an insulating film
Claim 5
Independent Claim 235 words
A method of manufacturing a semiconductor device, comprising the processes of: forming first and second well regions, which are of first and second conductivity types, respectively, in a semiconductor body; forming a gate insulation film on one side of each of the first and second well regions; forming a base layer of the second conductivity type on one side of the first well region; forming a contact hole in that part of the gate insulation film which is located on the base layer, thereby exposing part of the base layer; forming a polysilicon film on the gate insulation film and on an exposed part of the base layer; forming an emitter layer by introducing impurities of the first conductivity type into the base layer through the polysilicon film located on the exposed part of the base layer; ion-implanting impurities of the first conductivity type into an interface between the polysilicon film and the emitter layer, thereby breaking down an insulating film at the interface; removing a composite film, which includes the gate insulating film and the polysilicon film located on the second well region, such that the composite film remains in part on the second well region; ion-implanting impurities of the first conductivity type into the second well region, using the remaining composite film as a mask, thereby forming source and drain layers; and covering one side of the well regions with an insulating film
Claim 6
Dependent Claim 38 words
A method of manufacturing a semiconductor device according to claim 3, wherein the process of forming the emitter layer includes a step of ion-implanting impurities of the first conductivity type into the base layer through the polysilicon film.
Claim 7
Dependent Claim 94 words
A method of manufacturing a semiconductor device according to claim 3, further comprising the processes of: forming a third well region of the first conductivity type in the semiconductor body such that the third well region is isolated from the first well region by an isolating layer of the second conductivity type; and ion-implanting impurities of the second conductivity type into the first and third well regions, thereby simultaneously forming both a high-concentration impurity layer in the base layer of the first well region and source and drain layers in the third well region.
Claim 8
Independent Claim 223 words
A method of manufacturing a semiconductor device, comprising the processes of: forming first and second well regions, which are of first and second conductivity types, respectively, in a semiconductor body; forming a gate insulation film on one side of each of the first and second well regions; forming a base layer of the second conductivity type on one side of the first well region; forming a polysilicon film on the gate insulation removing a composite film, which includes the gate insulation film and the polysilicon film located on the second well region, such that the composite film remains in part on the second well region; introducing impurities of the first conductivity type into the second well region, using the remaining composite film as a mask, thereby forming source and drain layers; covering one side of the semiconductor body with an insulating film; forming a contact hole in those portions of the insulating film which are located on the base and source layers; forming an emitter layer of the first cond.uctivity type in the source layer located in the contact hole; covering portions exposed by the contact holes with a polysilicon film; and ion-implanting impurities of the first conductivity type into an interface between the portions exposed by the contact holes and the polysilicon film, thereby breaking down an insulating layer at the interface.
Claim 9
Independent Claim 223 words
A method of manufacturing a semiconductor device, comprising the processes of: forming first and second well regions, which are of first and second conductivity types, respectively, in a semiconductor body; forming a gate insulation film on one side of each of the first and second well regions; forming a base layer of the second conductivity type on one side of the first well region; forming a polysilicon film on the gate insulation removing a composite film, which includes the gate insulation film and the polysilicon film located on the second well region, such that the composite film remains in part on the second well region; introducing impurities of the first conductivity type into the second well region, using the remaining composite film as a mask, thereby forming source and drain layers; covering one side of the semiconductor body with an insulating film; forming a contact hole in those portions of the insulating film which are located on the base and source layers; forming an emitter layer of the first cond.uctivity type in the source layer located in the contact hole; covering portions exposed by the contact holes with a polysilicon film; and ion-implanting impurities of the first conductivity type into an interface between the portions exposed by the contact holes and the polysilicon film, thereby breaking down an insulating layer at the interface.
Claim 10
Dependent Claim 42 words
A method of manufacturing a semiconductor device according to claim 6, wherein the process of forming the emitter layer is performed before or after the insulating layer at the interface is broken down, or during the insulating layer is being broken down.

References Cited (Backward Citations)

US4403395A Cited
US4534806A Cited
US4346512A Cited
US4437897A Cited
US4484388A Cited
US4525922A Cited
US4640721A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-09-06 1992-03-07 1992-09-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-09-06 1996-03-07 1996-09-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-09-06 2000-03-07 2000-09-06 $7700.00 Window Closed / Lapsed

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