US4525922A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of producing a semiconductor device
Assignee: Fujitsu Ltd
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Filing: 1983-10-21
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Granted: 1985-07-02
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Expires: 2003-10-21
Abstract
Abstract A method of producing a semiconductor device, including a bipolar transistor and a Schottky barrier diode (e.g., an SBD transistor), includes the steps of selectively etching an insulating layer formed on an N-type silicon epitaxial layer so as to form an emitter electrode contact window; and forming a polycrystalline silicon layer on the exposed portion of a P-type base region in the window. The method further includes the steps of introducing N-type impurities into the P-type base region through the polycrystalline silicon layer in the window, selectively etching the insulating layer so as to form a base electrode contact window and a contact window for the electrode of the SBD and carrying out a heat treatment for redistribution of the introduced impurities so as to form an emitter region. An emitter electrode is then formed on the polycrystalline silicon layer and the electrode of the SBD is formed directly on the silicon epitaxial layer.
Inventors
- 👤 Tadashi Kiriseko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:45
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/34; H10D48/345; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/611; H10D84/613; H10D84/617
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
235 words
A method of producing a semiconductor device comprising a Schottky barrier diode and a bipolar transistor formed in a semiconductor substrate having an N-type silicon layer formed on the semiconductor substrate and having a P-type base region formed in the N-type silicon layer, the bipolar transistor having an emitter region formed by self-alignment with an emitter electrode contact window and having an emitter electrode connected to the emitter region through a polycrystalline silicon layer formed on the P-type base region, said method comprising the steps of: (a) selectively etching an insulating layer which is formed on the N-type silicon layer so as to form the emitter electrode contact window in which a portion of the P-type base region is exposed; (b) forming the polycrystalline silicon layer on at least the exposed portion of the P-type base region formed on the emitter electrode contact window; (c) introducing N-type impurities into the P-type base region through the polycrystalline silicon layer formed on the emitter electrode contact window; and (d) defining a base electrode contact window after said step (c) of introducing N-type impurities, in which a portion of the P-type base region is exposed, and defining a contact window for the electrode of the Schottky barrier diode in which a portion of the N-type silicon layer is exposed, by selectively etching through the polycrystalline silicon layer and the insulating layer using a resist layer as a mask.
Claim 2
Independent Claim
235 words
A method of producing a semiconductor device comprising a Schottky barrier diode and a bipolar transistor formed in a semiconductor substrate having an N-type silicon layer formed on the semiconductor substrate and having a P-type base region formed in the N-type silicon layer, the bipolar transistor having an emitter region formed by self-alignment with an emitter electrode contact window and having an emitter electrode connected to the emitter region through a polycrystalline silicon layer formed on the P-type base region, said method comprising the steps of: (a) selectively etching an insulating layer which is formed on the N-type silicon layer so as to form the emitter electrode contact window in which a portion of the P-type base region is exposed; (b) forming the polycrystalline silicon layer on at least the exposed portion of the P-type base region formed on the emitter electrode contact window; (c) introducing N-type impurities into the P-type base region through the polycrystalline silicon layer formed on the emitter electrode contact window; and (d) defining a base electrode contact window after said step (c) of introducing N-type impurities, in which a portion of the P-type base region is exposed, and defining a contact window for the electrode of the Schottky barrier diode in which a portion of the N-type silicon layer is exposed, by selectively etching through the polycrystalline silicon layer and the insulating layer using a resist layer as a mask.
Claim 3
Dependent Claim
92 words
A method according to claim 1, wherein said etching step (a) comprises the substep of etching the insulating layer to form a collector electrode contact window in which a portion of the N-type silicon layer is exposed, wherein said forming step (b) comprises the substep of forming the polycrystalline silicon layer on the exposed portion of the N-type silicon layer, and wherein said impurity introducing step (c) comprises the substep of introducing the N-type impurities into the N-type silicon layer through the polycrystalline silicon layer formed on the collector electrode contact window.
Claim 4
Dependent Claim
32 words
A method according to claim 1, further comprising a step (e) which comprises carrying out a heat treatment for redistribution of the N-type impurities so as to form an N-type emitter region.
Claim 5
Dependent Claim
36 words
A method according to claim 3, further comprising the step (f), after said heat-treating step (e), of forming, from a metal, an emitter electrode, a base electrode, a collector electrode and a Schottky barrier diode electrode.
Claim 6
Dependent Claim
35 words
A method according to claim 4, wherein said step (f) comprises forming the emitter, base, collector and Schottky barrier diode electrodes from a metal selected from the group consisting of aluminum, platinum silicide and titanium.
Claim 7
Dependent Claim
19 words
A method according to claim 1, wherein said impurity introducing step (c) comprises introducing impurities using an ion implantation.
Claim 8
Dependent Claim
24 words
A method according to claim 1, wherein said step (c) comprises introducing N-type impurities selected from the group consisting of arsenic, phosphorus and antimony.
Claim 9
Dependent Claim
26 words
A method according to claim 1, further comprising forming the semiconductor substrate of a P-type silicon single crystalline substrate and forming the N-type silicon layer thereon.
Claim 10
Dependent Claim
18 words
A method according to claim 1, wherein said step (a) comprises forming the insulating layer of silicon dioxide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-01 | 1988-12-31 | 1989-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-01 | 1992-12-31 | 1993-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-01 | 1996-12-31 | 1997-07-02 | $7700.00 | Window Closed / Lapsed |