US4418468A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for fabricating a logic structure utilizing polycrystalline silicon Schottky diodes
Assignee: National Semiconductor Corp
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Filing: 1981-05-08
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Granted: 1983-12-06
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Expires: 2001-05-08
Abstract
Abstract An integrated circuit structure and process for fabricating it are described which allow fabrication of a very compact high-speed logic gate. The structure utilizes a bipolar transistor formed in an epitaxial silicon pocket surrounded by silicon dioxide. A pair of Schottky diodes and a resistor are formed outside the epitaxial pocket on the silicon dioxide and connected to the pocket by doped polycrystalline silicon.
Inventors
- 👤 Madhukar B. Vora
- 👤 Hermaj K. Hingarh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:09
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/084; H03K19/0846; H10D62/00; H10D62/40; H10D8/00; H10D8/60; H10D88/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
118 words
A process for fabricating an integrated circuit comprising: fabricating a pocket of semiconductor material surrounded by insulating material; depositing a layer of a metal silicide on a first region of the insulating material; depositing a first layer of semiconductor material on the layer of metal silicide; and forming selected portions of a second layer of semiconductor material over at least a second region of the insulating material, the first layer of semiconductor material, and selected portions of the pocket, at least those portions of the second layer extending from the first layer to the pocket and from the pocket to the second region having higher impurity doping than that portion of the second layer overlying the second region.
Claim 2
Dependent Claim
118 words
A process for fabricating an integrated circuit comprising: fabricating a pocket of semiconductor material surrounded by insulating material; depositing a layer of a metal silicide on a first region of the insulating material; depositing a first layer of semiconductor material on the layer of metal silicide; and forming selected portions of a second layer of semiconductor material over at least a second region of the insulating material, the first layer of semiconductor material, and selected portions of the pocket, at least those portions of the second layer extending from the first layer to the pocket and from the pocket to the second region having higher impurity doping than that portion of the second layer overlying the second region.
Claim 3
Dependent Claim
25 words
A process as in claim 1 wherein: the insulating material comprises oxidized silicon; and the first and the second layers of semiconductor material comprise silicon.
Claim 4
Dependent Claim
16 words
A process as in claim 2 wherein the first and the second layers comprise polycrystalline silicon.
Claim 5
Dependent Claim
44 words
A process as in claim 1 wherein the step of forming selected portions of a second layer comprises: depositing lightly doped semiconductor material; doping those portions of the second layer which have a higher impurity doping; and removing undesired regions of the second layer.
Claim 6
Dependent Claim
30 words
A process as in claim 4 wherein the second layer is deposited over all of the pocket and the insulating material and then removed from over part of the pocket.
Claim 7
Dependent Claim
19 words
A process as in claim 1 further including the step of fabricating at least one transistor in the pocket.
Claim 8
Dependent Claim
27 words
A process as in claim 6 wherein a third region of the second layer is separated from the pocket by the second region of the second layer.
Claim 9
Dependent Claim
30 words
A process as in claim 7 further including the step of fabricating electrical connections of the third region, the at least one transistor, and the first layer of semiconductor material.
Claim 10
Dependent Claim
28 words
A process as in claim 1 wherein the first layer of semiconductor material is more heavily doped than the portion of the second layer overlying the second region.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-05 | 1987-06-06 | 1987-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-05 | 1991-06-06 | 1991-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-05 | 1995-06-06 | 1995-12-06 | $7700.00 | Window Closed / Lapsed |