US4721682A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Isolation and substrate connection for a bipolar integrated circuit
Assignee: Advanced Micro Devices Inc
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Filing: 1985-09-25
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Granted: 1988-01-26
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Expires: 2005-09-25
Abstract
Abstract A structure for isolating a bipolar transistor (100) from an adjacent transistor includes a first silicon dioxide isolation region (110) laterally surrounding the transistor and a conductive channel stop region (112) laterally surrounding the silicon dioxide isolation region. The channel stop region allows electrical potential of the substrate (102) to be controlled and the silicon dioxide isolation region prevents the channel stop from contacting the transistor.
Inventors
- 👤 Scott O. Graham
- 👤 Lawrence Y. Lin
- 👤 Hua T. Chua
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:51
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/10; H10W20/00; H10W20/01; H10W20/021
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
96 words
A method for forming a transistor comprising: forming an epitaxial layer of a first conductivity type on a substrate of a second conductivity type opposite to said first conductivity type; forming a transistor in said epitaxial layer; forming a nonconductive region laterally surrounding said transistor, said nonconductive region extending from the surface of said epitaxial layer to said substrate; and doping a portion of said epitaxial layer so that said doped portion is of said second conductivity type, said doped portion contacting said subtrate, said doped portion of said epitaxial layer laterally surrounding said nonconductive region.
Claim 2
Independent Claim
96 words
A method for forming a transistor comprising: forming an epitaxial layer of a first conductivity type on a substrate of a second conductivity type opposite to said first conductivity type; forming a transistor in said epitaxial layer; forming a nonconductive region laterally surrounding said transistor, said nonconductive region extending from the surface of said epitaxial layer to said substrate; and doping a portion of said epitaxial layer so that said doped portion is of said second conductivity type, said doped portion contacting said subtrate, said doped portion of said epitaxial layer laterally surrounding said nonconductive region.
Claim 3
Independent Claim
127 words
A method comprising the steps of: forming an epitaxial layer of semiconductor material of a first conductivity type on a substrate of a second conductivity type opposite of said first conductivity type; forming a plurality of transistors in said epitaxial layer; forming a plurality of nonconductive regions, each nonconductive region within said plurality laterally surrounding an associated one of said transistors within said plurality of transistors, each of said nonconductive regions within said plurality of nonconductive regions being laterally surrounded by a portion of said epitaxial layer; and doping the portions of said epitaxial layer laterally surrounding said nonconductive regions within said plurality of nonconductive regions so that said portions of said epitaxial layer are of said second conductivity type and said portions electrically contact said substrate.
Claim 4
Independent Claim
127 words
A method comprising the steps of: forming an epitaxial layer of semiconductor material of a first conductivity type on a substrate of a second conductivity type opposite of said first conductivity type; forming a plurality of transistors in said epitaxial layer; forming a plurality of nonconductive regions, each nonconductive region within said plurality laterally surrounding an associated one of said transistors within said plurality of transistors, each of said nonconductive regions within said plurality of nonconductive regions being laterally surrounded by a portion of said epitaxial layer; and doping the portions of said epitaxial layer laterally surrounding said nonconductive regions within said plurality of nonconductive regions so that said portions of said epitaxial layer are of said second conductivity type and said portions electrically contact said substrate.
Claim 5
Independent Claim
115 words
A method comprising the steps of: forming a first region of semiconductor material having a first conductivity type above a second region of semiconductor material having a second conductivity type opposite to said first conductivity type, said first region having a top surface; forming a transistor in said first region of semiconductor material; forming a nonconductive region laterally surrounding said transistor, said nonconductive region extending from said top surface of said first region to said second region; and doping a portion of said first region so that said doped portion is of said second conductivity type, said doped portion contacting said second region, said doped portion of said first region laterally surrounding said nonconductive region.
Claim 6
Independent Claim
115 words
A method comprising the steps of: forming a first region of semiconductor material having a first conductivity type above a second region of semiconductor material having a second conductivity type opposite to said first conductivity type, said first region having a top surface; forming a transistor in said first region of semiconductor material; forming a nonconductive region laterally surrounding said transistor, said nonconductive region extending from said top surface of said first region to said second region; and doping a portion of said first region so that said doped portion is of said second conductivity type, said doped portion contacting said second region, said doped portion of said first region laterally surrounding said nonconductive region.
Claim 7
Dependent Claim
137 words
A process comprising the steps of: providing a first region of semiconductor material above a second region of semiconductor material, said second region having a first conductivity type, said first region having a top surface; forming a transistor in a first portion of said first region; forming a nonconductive region laterally surrounding said transistor, said nonconductive region extending from said top surface to said second region; and wherein at the conclusion of said process, said nonconductive region is laterally surrounded by a second portion of said first region, said second portion extending to said second region, said second portion having said first conductivity type, and wherein at the conclusion of said process, the part of said first portion of said first region adjacent to said second region has a second conductivity type opposite said first conductivity type.
Claim 8
Dependent Claim
137 words
A process comprising the steps of: providing a first region of semiconductor material above a second region of semiconductor material, said second region having a first conductivity type, said first region having a top surface; forming a transistor in a first portion of said first region; forming a nonconductive region laterally surrounding said transistor, said nonconductive region extending from said top surface to said second region; and wherein at the conclusion of said process, said nonconductive region is laterally surrounded by a second portion of said first region, said second portion extending to said second region, said second portion having said first conductivity type, and wherein at the conclusion of said process, the part of said first portion of said first region adjacent to said second region has a second conductivity type opposite said first conductivity type.
Claim 9
Dependent Claim
65 words
The method of claim 4 further comprising the step of forming electrically conductive material on said second portion of said first region, said electrically conductive material electrically contacting said second portion of said first region, said second portion of said first region electrically contacting said second region, so that said electrically conductive material permits a selected electrical potential to be applied to said second region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-25 | 1991-07-27 | 1992-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-25 | 1995-07-27 | 1996-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-25 | 1999-07-27 | 2000-01-26 | $7700.00 | Window Closed / Lapsed |