MOS transistor circuits having matched channel width and length dimensions

Claim 1

A circuit arrangement including first and second voltage supply terminals between which the voltage supply is to be applied, an input terminal to which an input signal is to be applied, and an output terminal at which an output signal is to be derived, and first, second and third amplifier stages, each stage including a driver transistor and a load transistor, each transistor being of the enhancement node type and including a source and a drain spaced by a channel and an insulated gate overlying the channel, the drive and load transistors of each stage having equal channel lenghts and widths, in each stage the source of the driver transistor being connected to the first voltage supply terminal, the drain of the driver transistor being connected to the source of the load transistor at a source-drain node, the drain of the load transistor being connected to the second voltage supply terminal, and the gate of the driver transistor being connected to the input terminal, in the first stage, the gate of the load transistor being connected to the drain of the load transistor, in the second stage, the gate of the load transistor being connected to the source-drain node of the first stage, in the third stage, the gate of the load transistor being connected to the source-drain node of the second stage, and the source-drain node of the third stage being connected to the output terminal.