US3898477A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self ratioing input buffer circuit
Assignee: Motorola Solutions Inc
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Filing: 1974-06-03
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Granted: 1975-08-05
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Expires: 1994-06-03
Abstract
Abstract An MOS inverter which may be used as an input buffer on an integrated circuit chip includes a first load MOSFET having its gate and drain coupled to a supply conductor and a second MOSFET load device coupled between the supply conductor and the output terminal of the input buffer. The gate of the second MOSFET load device is connected to the output of a MOSFET bias circuit coupled between the voltage supply conductor and the ground conductor. The bias circuitry establishes a bias potential such that the inverter ratio of the input buffer varies as a function of MOSFET processing parameters by reducing the inverter ratio at low MOSFET threshold voltages and increasing the inverter ratio at high MOSFET threshold voltages, thereby improving the noise immunity and speed of the circuit.
Inventors
- 👤 John K Buchanan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/003; H03K19/00369; H03K19/00384; H03K19/0175; H03K19/0185; H03K19/018507
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
111 words
A semiconductor circuit including an output, first and second voltage conductors, a load circuit and a switching circuit coupled in series between said first and second voltage conductors comprising: logic switching means in said switching circuit coupled between said second voltage conductor and said output; first load means in said load circuit coupled between said first voltage conductor and said output; and second load means coupled between said first voltage conductor and said output for controlling the ratio of the effective channel width-to-length ratio of said switching circuit of said circuit to the effective channel width-to-length ratio of said load circuit as a function of semiconductor processing parameters of said circuit.
Claim 2
Dependent Claim
111 words
A semiconductor circuit including an output, first and second voltage conductors, a load circuit and a switching circuit coupled in series between said first and second voltage conductors comprising: logic switching means in said switching circuit coupled between said second voltage conductor and said output; first load means in said load circuit coupled between said first voltage conductor and said output; and second load means coupled between said first voltage conductor and said output for controlling the ratio of the effective channel width-to-length ratio of said switching circuit of said circuit to the effective channel width-to-length ratio of said load circuit as a function of semiconductor processing parameters of said circuit.
Claim 3
Dependent Claim
59 words
The semiconductor circuit as recited in claim 1 further including transistor bias circuit means coupled between said first and second voltage conductors for establishing a threshold voltage level at which said second load means begins current conduction as a function of a semiconductor processing parameter of said semiconductor circuit coupled to a control element of said second load means.
Claim 4
Dependent Claim
45 words
The semiconductor circuit as recited in claim 2 wherein said first load means and said second load means each comprises a MOSFET, and said logic switching means includes a switching MOSFET coupled between the source of said first load MOSFET and said voltage conductor means.
Claim 5
Dependent Claim
24 words
The semiconductor circuit as recited in claim 3 wherein said first load MOSFET has its gate and drain coupled to said voltaGe conductor means.
Claim 6
Dependent Claim
41 words
The semiconductor circuit as recited in claim 4 wherein said bias circuit means includes first and second MOSFETs coupled in series between said first and second voltage conductor, the gate of said second MOSFET being connected to said first voltage conductor.
Claim 7
Dependent Claim
22 words
The semiconductor circuit as recited in claim 5 wherein the gate of said first MOSFET is coupled to said first voltage conductor.
Claim 8
Dependent Claim
163 words
An input buffer of the inverter type on a MOSFET integrated circuit chip connected between first and second voltage conductors and having an input terminal coupled to an input bonding pad and an output terminal coupled to other MOS circuitry on said integrated circuit chip and means for adjusting the inverter ratio of said input buffer as a function of the MOS threshold voltage comprising: a first MOSFET coupled between said second voltage conductor and said output terminal of said input buffer and having its gate coupled to said input bonding pad; a second MOSFET coupled between said first voltage conductor and said output terminal having its gate connected to its drain; a third MOSFET coupled between said first voltage conductor and said output terminal; a MOSFET bias circuit having an output terminal coupled to control said third MOSFET and coupled between said first and second voltage conductors for establishing a bias voltage for controlling the characteristic inverter ratio of said input buffer.
Claim 9
Dependent Claim
163 words
An input buffer of the inverter type on a MOSFET integrated circuit chip connected between first and second voltage conductors and having an input terminal coupled to an input bonding pad and an output terminal coupled to other MOS circuitry on said integrated circuit chip and means for adjusting the inverter ratio of said input buffer as a function of the MOS threshold voltage comprising: a first MOSFET coupled between said second voltage conductor and said output terminal of said input buffer and having its gate coupled to said input bonding pad; a second MOSFET coupled between said first voltage conductor and said output terminal having its gate connected to its drain; a third MOSFET coupled between said first voltage conductor and said output terminal; a MOSFET bias circuit having an output terminal coupled to control said third MOSFET and coupled between said first and second voltage conductors for establishing a bias voltage for controlling the characteristic inverter ratio of said input buffer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-04 | 1979-02-03 | 1979-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-04 | 1983-02-03 | 1983-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-04 | 1987-02-03 | 1987-08-05 | $7700.00 | Window Closed / Lapsed |