US3564299A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock generator
Assignee: Arris Technology Inc
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Filing: 1969-01-16
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Granted: 1971-02-16
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Expires: 1989-01-16
Abstract
Abstract A clock generator develops an output timing signal from two input signals having a time interval therebetween. A clamping device controlled by the input signals is effective to maintain said output signal at its desired level during the interval between the input signals, and means are provided to maintain the voltage level at the input node at an appropriate level during that interval.
Inventors
- 👤 Andrew G Varadi
- 👤 Richard B Rubinstein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:47
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K5/00; H03K5/01; H03K5/04; H03K5/05; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/0015; H03K2005/00195
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
154 words
In a clock circuit for generating an output signal having first and second levels from first and second sequential input signals having a time interval therebetween, said circuit comprising an input node, and output node at which said output signal is to be developed, first and second potential sources at said first and second levels respectively, first switch means effective when actuated to operatively connect said output noDe to said first potential source; the improvement which comprises, conductive means effective to connect said input node to said first potential source in the interval between said first and second input signals, and second switch means being effective to operatively connect said input node and said output node to said second potential source thereby to deactuate said first switch means to operatively disconnect said input node form said first potential source during said second input signal, and to charge said output node to said second level.
Claim 2
Dependent Claim
154 words
In a clock circuit for generating an output signal having first and second levels from first and second sequential input signals having a time interval therebetween, said circuit comprising an input node, and output node at which said output signal is to be developed, first and second potential sources at said first and second levels respectively, first switch means effective when actuated to operatively connect said output noDe to said first potential source; the improvement which comprises, conductive means effective to connect said input node to said first potential source in the interval between said first and second input signals, and second switch means being effective to operatively connect said input node and said output node to said second potential source thereby to deactuate said first switch means to operatively disconnect said input node form said first potential source during said second input signal, and to charge said output node to said second level.
Claim 3
Dependent Claim
28 words
In the circuit of claim 1, in which said conductive means comprises a resistor having a greater resistance value than the conducting resistance of said second switch means.
Claim 4
Dependent Claim
47 words
In the circuit of claim 2, in which said circuit is formed on a chip of semiconductor substrate material of a given polarity, said resistor being defined by a region of semiconductor material on said chip of a polarity opposite to the polarity of said substrate material.
Claim 5
Dependent Claim
104 words
The circuit of claim 1, in which said second switch means comprises a first switch device operatively connected between said output node and said second potential source and effective when actuated to connect said output node to said second potential source, thereby to charge said output node to said second level, and a second switch device operatively connected between said input node and said second potential source and effective when actuated to connect said input node to said second potential source, thereby to charge said input node to said second level, said first and second switch devices being actuated by said second input signal.
Claim 6
Dependent Claim
104 words
The circuit of claim 3, in which said second switch means comprises a first switch device operatively connected between said output node and said second potential source and effective when actuated to connect said output node to said second potential source, thereby to charge said output node to said second level, and a second switch device operatively connected between said input node and said second potential source and effective when actuated to connect said input node to said second potential source, thereby to charge said input node to said second level, said first and second switch devices being actuated by said second input signal.
Claim 7
Dependent Claim
72 words
The circuit of claim 4 further comprising third switch means operatively connected between said input node and said second potential source, and effective when actuated to connect said input node to said second potential source, and means for actuating said third switch means in the interval between said second input signal and the next succeeding first input signal, thereby to charge said input node to said second level during said last-mentioned interval.
Claim 8
Dependent Claim
73 words
The circuit of claim 5, further comprising third switch means operatively connected between said input node and said second potential source, and effective when actuated to connect said input node to said second potential source, and means for actuating said third switch means in the interval between said second input signal and the next succeeding first input signal, thereby to charge said input node to said second level during said last mentioned interval.
Claim 9
Dependent Claim
81 words
In the circuit of claim 6 said actuating means further comprising a second output node, means for generating a second output signal at said second output node beginning at the onset of said second input signal and terminating at the onset of the next succeeding first input signal, and means for applying said second output signal to said third switch means, thereby to actuate the latter and to charge said input node to said second level during said second output signal.
Claim 10
Dependent Claim
81 words
In the circuit of claim 7, said actuating means further comprising a second output node, means for generating a second output signal at said second output node beginning at the onset of said second input signal and terminating at the onset of the next succeeding first input signal, and means for applying said second output signal to said third switch means, thereby to actuate the latter and to charge said input node to said second level during said second output signal.
Claim 11
Dependent Claim
82 words
In the circuit of claim 1, further comprising a third output node, and means for developing a third output signal at said third output node, said last mentioned means comprising second conductive means operatively connecting said third output node to said first potential source, and fourth, fifth, and sixth switch means respectively actuated by said first and second input signals and said second output signal, and effective when so actuated to operatively connect said third output node to said second potential source.
Claim 12
Dependent Claim
16 words
In the circuit of claim 10, in which said second conductive means comprises a second resistor.
Claim 13
Dependent Claim
24 words
In the circuit of claim 11, in which said second resistor is defined by a second region of semiconductor material formed on said chip.
Claim 14
Dependent Claim
79 words
In the circuit of claim 8, a third output node, and means for developing a third output signal at said third output node, said last mentioned means comprising second conductive means operatively connecting said third output node to said first potential source, and four, fifth, and sixth switch means respectively actuated by said first and second input signals and said second output signal, and effective when so actuated to operatively connect said third output node to said second source.
Claim 15
Dependent Claim
14 words
In the circuit of claim 13, said second conductive means comprising a second resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-15 | 1974-08-17 | 1975-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-15 | 1978-08-17 | 1979-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-15 | 1982-08-17 | 1983-02-16 | $7700.00 | Window Closed / Lapsed |