US3845324A — Dual voltage fet inverter circuit with two level …

Claim 1

Independent Claim 353 words

A logic circuit having input and output terminals comprising: first switching means having first and second terminals with a variable resistive path defined therebetween, and an actuable control terminal for selectively switching said path from a first state exhibiting a relatively high value of resistance to a second state exhibiting a relatively low value of resistance, said first terminal being connected to the output terminal, said second terminal being connected to a circuit ground return, and said control terminal being connected to the input terminal, a first voltage source producing a substantially constant low level bias voltage, a field-effect load transistor having source, drain and gate electrodes, respectively, said drain electrode being connected to said first low level voltage source and said source electrode being connected to the output terminal, a second substantially constant voltage source for producing on the gate electrode of said load transistor a bias voltage at a level higher than that of said first voltage source, capacitor means connected between said source electrode and said gate electrode of said load transistor, and having charging and discharging states respectively responsive to the relatively low and high resistance switching states of said first switching means, said capacitor means feeding back output voltage to the gate electrode of said load transistor at the beginning of each high resistance state of said first switching means, said feedback voltage being sufficient, when combined with the voltage supplied by said second voltage source, to produce a substantial overdriving gate-to-source electrode voltage differential so as to produce a rapid output signal transition in the direction toward and reaching the voltage level of the drain electrode of said load transistor, second switching means connected between said second voltage source and said gate electrode of said load transistor for establishing a relatively low resistance interconnection therebetween during, and in response to, each successive period when the path of said first switching means exhibits a low resistance state, and for establishing said interconnection as a relatively high resistance during, and in response to, each successive period when the path of said first switching means exhibits a high resistance state.

Claim 2

Dependent Claim 353 words

A logic circuit having input and output terminals comprising: first switching means having first and second terminals with a variable resistive path defined therebetween, and an actuable control terminal for selectively switching said path from a first state exhibiting a relatively high value of resistance to a second state exhibiting a relatively low value of resistance, said first terminal being connected to the output terminal, said second terminal being connected to a circuit ground return, and said control terminal being connected to the input terminal, a first voltage source producing a substantially constant low level bias voltage, a field-effect load transistor having source, drain and gate electrodes, respectively, said drain electrode being connected to said first low level voltage source and said source electrode being connected to the output terminal, a second substantially constant voltage source for producing on the gate electrode of said load transistor a bias voltage at a level higher than that of said first voltage source, capacitor means connected between said source electrode and said gate electrode of said load transistor, and having charging and discharging states respectively responsive to the relatively low and high resistance switching states of said first switching means, said capacitor means feeding back output voltage to the gate electrode of said load transistor at the beginning of each high resistance state of said first switching means, said feedback voltage being sufficient, when combined with the voltage supplied by said second voltage source, to produce a substantial overdriving gate-to-source electrode voltage differential so as to produce a rapid output signal transition in the direction toward and reaching the voltage level of the drain electrode of said load transistor, second switching means connected between said second voltage source and said gate electrode of said load transistor for establishing a relatively low resistance interconnection therebetween during, and in response to, each successive period when the path of said first switching means exhibits a low resistance state, and for establishing said interconnection as a relatively high resistance during, and in response to, each successive period when the path of said first switching means exhibits a high resistance state.

Claim 3

Dependent Claim 43 words

An inverter circuit in accordance with claim 1 wherein said field-effect load transistor is of the MOSFET type, and wherein said first switching means also comprises a MOSFET, with said control, first and second terminals thereof comprising gate, drain, and source electrodes, respectively.

Claim 4

Dependent Claim 86 words

the higher supply voltage is connected to the input terminal of the biasing means so as to provide a biasing voltage applied to the gate when said switching means is ON, the magnitude of the higher supply voltage being selected to provide such a biasing voltage to the gate which is greater than the magnitude of the lower supply voltage by at least the threshold voltage drop of the transistor, and which is also sufficient to turn the transistor ON when the switching means is ON;

Claim 5

Dependent Claim 86 words

the higher supply voltage is connected to the input terminal of the biasing means so as to provide a biasing voltage applied to the gate when said switching means is ON, the magnitude of the higher supply voltage being selected to provide such a biasing voltage to the gate which is greater than the magnitude of the lower supply voltage by at least the threshold voltage drop of the transistor, and which is also sufficient to turn the transistor ON when the switching means is ON;

Claim 6

Dependent Claim 56 words

An inverter circuit in accordance with claim 2 wherein said second switching means also comprises a MOSFET having a gate, a drain, and a source electrode, with both the drain and gate electrodes thereof being connected to said second voltage source, and said associated source electrode being connected to the gate electrode of said load transistor.

Claim 7

Dependent Claim 130 words

The lower supply voltage is connected to the first controlled terminal of the transistor, the magnitude of the lower supply voltage being selected to provide a useable output voltage through the transistor to the output terminal when the switching means is OFF, the lOwer supply voltage serving through the transistor and the feedback means to provide a kicker voltage as recited in clause (D) which is lower than the biasing voltage applied to the gate electrode by the biasing means, the combination of the relatively higher biasing voltage and the relatively lower kicker voltage serving to overdrive the gate of the transistor to accelerate the response time of the transistor when the switching means turns OFF, while minimizing the power dissipation to ground resulting when the switching means is ON.

Claim 8

Dependent Claim 130 words

The lower supply voltage is connected to the first controlled terminal of the transistor, the magnitude of the lower supply voltage being selected to provide a useable output voltage through the transistor to the output terminal when the switching means is OFF, the lOwer supply voltage serving through the transistor and the feedback means to provide a kicker voltage as recited in clause (D) which is lower than the biasing voltage applied to the gate electrode by the biasing means, the combination of the relatively higher biasing voltage and the relatively lower kicker voltage serving to overdrive the gate of the transistor to accelerate the response time of the transistor when the switching means turns OFF, while minimizing the power dissipation to ground resulting when the switching means is ON.

Claim 9

Dependent Claim 233 words

An inverter circuit comprising: a first substantially constant low level voltage source, a second substantially constant voltage source prOducing a voltage level higher than that of said first source, a first field-effect transistor having first and second electrodes and a gate electrode, with at least said gate electrode being connected to said second voltage source, and said first electrode being biased to a level not less than the threshold drop of said first transistor relative to the level of said second voltage source, a second field-effect transistor having first and second electrodes and a gate electrode, the first electrode being connected to said first voltage source, and the gate electrode thereof being connected to the second electrode of said first transistor, a third input signal responsive field-effect transistor having first and second electrodes and a gate electrode, with said first electrode thereof being connected to the second electrode of said second transistor, and with said defined interconnection further providing an output, said gate electrode of said third transistor functioning as an input signal terminal, and, positive feedback means connected between said second electrode of said second transistor and said gate electrode thereof, said feedback means feeding back to the gate electrode of said second transistor at least a portion of the output signal established during each successive period in which an input signal has a voltage level which turns OFF said third transistor.

Claim 10

Dependent Claim 233 words

An inverter circuit comprising: a first substantially constant low level voltage source, a second substantially constant voltage source prOducing a voltage level higher than that of said first source, a first field-effect transistor having first and second electrodes and a gate electrode, with at least said gate electrode being connected to said second voltage source, and said first electrode being biased to a level not less than the threshold drop of said first transistor relative to the level of said second voltage source, a second field-effect transistor having first and second electrodes and a gate electrode, the first electrode being connected to said first voltage source, and the gate electrode thereof being connected to the second electrode of said first transistor, a third input signal responsive field-effect transistor having first and second electrodes and a gate electrode, with said first electrode thereof being connected to the second electrode of said second transistor, and with said defined interconnection further providing an output, said gate electrode of said third transistor functioning as an input signal terminal, and, positive feedback means connected between said second electrode of said second transistor and said gate electrode thereof, said feedback means feeding back to the gate electrode of said second transistor at least a portion of the output signal established during each successive period in which an input signal has a voltage level which turns OFF said third transistor.

Claim 11

Dependent Claim 265 words

An improved logic circuit of the type including: A. switching means for selectively establishing either an ''''ON'''' (essentially short circuit condition) or an ''''OFF'''' (essentially open circuit condition) between first and second terminals thereof, said second terminal being connected to circuit ground; B. a field-effect transistor having a gate electrode and first and second controlled terminals, said first controlled terminal being connected to a supply voltage and said second controlled terminal being connected to the first terminal of said switching means and to an output terminal, so that the transistor when ON (1) conducts the supply voltage to ground through the switching means when the switching means is also ON, and (2) conducts the supply voltage to the output terminal when the switching means is OFF; C. voltage biasing means for turning the transistor ON, the biasing means having an input terminal, and an output terminal connected to said gate electrode of said transistor; and D. voltage feedback means connected between said second controlled terminal and said gate electrode of said transistor for feeding back to said gate electrode a kicker voltage related to the increase in output voltage at said output terminal when said switching means changes from ON to OFF, the kicker voltage adding to the voltage applied by the biasing means to overdrive the gate and augment the ON state of the transistor; wherein the improved circuit is characterized in that two distinct supply voltages are provided, both of the polarity required to turn the transistor ON, the supply voltages being connected in the circuit and related to each other as follows:

Claim 12

Dependent Claim 265 words

An improved logic circuit of the type including: A. switching means for selectively establishing either an ''''ON'''' (essentially short circuit condition) or an ''''OFF'''' (essentially open circuit condition) between first and second terminals thereof, said second terminal being connected to circuit ground; B. a field-effect transistor having a gate electrode and first and second controlled terminals, said first controlled terminal being connected to a supply voltage and said second controlled terminal being connected to the first terminal of said switching means and to an output terminal, so that the transistor when ON (1) conducts the supply voltage to ground through the switching means when the switching means is also ON, and (2) conducts the supply voltage to the output terminal when the switching means is OFF; C. voltage biasing means for turning the transistor ON, the biasing means having an input terminal, and an output terminal connected to said gate electrode of said transistor; and D. voltage feedback means connected between said second controlled terminal and said gate electrode of said transistor for feeding back to said gate electrode a kicker voltage related to the increase in output voltage at said output terminal when said switching means changes from ON to OFF, the kicker voltage adding to the voltage applied by the biasing means to overdrive the gate and augment the ON state of the transistor; wherein the improved circuit is characterized in that two distinct supply voltages are provided, both of the polarity required to turn the transistor ON, the supply voltages being connected in the circuit and related to each other as follows:

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1977-10-28	1978-04-29	1978-10-29	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1981-10-28	1982-04-29	1982-10-29	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1985-10-28	1986-04-29	1986-10-29	$7700.00	Window Closed / Lapsed

Dual voltage fet inverter circuit with two level biasing

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