Minor clock generator using major clock signals

Claim 2

A minor phase clock signal generator having an output and using major phase clock signals, said generator comprising, a first load field effect transistor means for setting the output to one logical level during the corresponding logical level of a first major phase clock signal, said first load field effect transistor means being connected between said output and said first major phase clock signal, a second field effect transistor connected between the output and a second major phase clock signal for setting the output to a second logical level during a corresponding logical level of said second major phase clock signal, a third field effect transistor connected between said first load field effect transistor means and said second major phase clock signal and having its gate electrode connected to said first major phase clock signal for turning said first load field effect transistor means off at the end of the first logical level of said second major phase clock signal.

Claim 3

The generator recited in claim 1 wherein said first and second major clock signals have overlapping phases.

Claim 4

The generator recited in claim 1 wherein said first load field effect transistor means and said second field effect transistor are relatively low resistance devices whereby the signal transitions of the output from one logical level to the other logical level closely approximate the transitions of said first and second major phase clock signals between said logic levels and whereby the separation of said minor phase clock signal from adjacent phases of said major phase clock signals is maintained.

Claim 5

The generator recited in claim 1 wherein said first load field effect transistor has its drain electrode connected to said first level phase clock signal and its source electrode connected to said output, said second and third field effect transistors have their gate electrodes connected to said first major phase clock signal and their drain electrodes connected to said second major phase clock signals, said source electrode of said second field effect transistor being connected to said output and said source electrode of said third field effect transistor being connected to the gate electrode of said first load field effect transistor means.

Claim 6

The generator recited in claim 1 and further including a feedback capacitor connected between the output and the gate electrode of said first load field effect transistor means for feeding back the output voltage to the gate electrode during said first logical level of the first major phase clock signal for boosting the output voltage to the voltage level of said first major phase clock signal, a fourth field effect transistor connected between an input voltage level and the common connection of said gate electrode and said capacitor for precharging said capacitor and for initially turning said first load field effect transistor means on before said output voltage is fed back.

Claim 7

The generator recited in claim 5 wherein the gate electrode of said fourth field effect transistor is connected to a third major phase clock signal, said first, second and third major phase clock signals being related in phase as a function of the phase of the minor phase clock signal.

Claim 8

The generator recited in claim 6 wherein when a phase 1 minor phase clock signal is required, said first and second major phase clock signals are phi 1 2 and phi 4 1, respectively, and said third major phase clock signal is phi 3 4, when a phase two minor phase clock signal is required, said first and second major phase clock signals are phi 2 3 and phi 1 2, respectiVely, and said third major phase clock signal is phi 4 1; and where a third minor phase clock signal is required said first and second major phase clock signals are phi 3 4 and phi 2 3, respectively, and said third major phase clock signal is phi 1 2 and when a fourth phase clock signal is required, said first and second major phase clock signals are phi 4 1 and phi 3 4, respectively, and said third major phase clock signal is phi 2 3.

Claim 9

A minor phase clock signal generator having an output and an input connected to a voltage level, said minor phase clock signal generator being gated by selected multiple phase clock signals, said generator comprising, a first field effect transistor having a gate electrode and having its source electrode connected to said output, and its drain electrode connected to a first major phase clock signal, a capacitor connected between the output and the gate electrode of said first field effect transistor for feeding back the output voltage during a selected interval for enhancing the conduction of said first field effect transistor, a second field effect transistor having its gate electrode connected to the first major phase clock signal, its source electrode connected to the output and its drain electrode connected to a second major phase clock signal, said first and second major phase clock signals having an overlapping phase, a third field effect transistor having its gate electrode connected to the first major phase clock signal, its source electrode connected to the gate electrode of said first field effect transistor, and its drain electrode connected to the second major phase clock signal, a fourth field effect transistor having its gate electrode connected to a third major phase clock signal, its drain electrode connected to the input and its source electrode connected to the gate electrode of said first field effect transistor, said third major phase clock signal having a phase which overlaps a phase of the second major phase clock signal without overlapping a phase of the first major phase clock signal.

Claim 10

A minor phase clock signal generator having an output and an input connected to a voltage level, said minor phase clock signal generator being gated by selected multiple phase clock signals, said generator comprising, a first field effect transistor having a gate electrode and having its source electrode connected to said output, and its drain electrode connected to a first major phase clock signal, a capacitor connected between the output and the gate electrode of said first field effect transistor for feeding back the output voltage during a selected interval for enhancing the conduction of said first field effect transistor, a second field effect transistor having its gate electrode connected to the first major phase clock signal, its source electrode connected to the output and its drain electrode connected to a second major phase clock signal, said first and second major phase clock signals having an overlapping phase, a third field effect transistor having its gate electrode connected to the first major phase clock signal, its source electrode connected to the gate electrode of said first field effect transistor, and its drain electrode connected to the second major phase clock signal, a fourth field effect transistor having its gate electrode connected to a third major phase clock signal, its drain electrode connected to the input and its source electrode connected to the gate electrode of said first field effect transistor, said third major phase clock signal having a phase which overlaps a phase of the second major phase clock signal without overlapping a phase of the first major phase clock signal.