Abstract An intermediate driver circuit comprising at least five stages which are cascaded between a signal driver, such as a logic circuit on an LSI chip, and a high capacity load driver, such as a driver for long off chip interconnection lines, wherein the total delay in the signal source caused by great disparity between the capacitance of the signal driver and the load driver is minimized. The delay is minimized by use of a cascaded series of n-intermediate drivers where n=1nM, ##EQU1## AND WHERE THE CAPACITANCE OF ANY INTERMEDIATE STAGE IS C P =√C.sub.(P -1 ) .sup.. C.sub.(P +1 ). Use of these parameters in the design of intermediate stages, each having a capacitance designed in accordance with the foregoing equations has been found to be useful in connection with amplifiers having five or more intermediate stages, and wherein the ratio of capacitance of the load circuit to the capacitance of the driver circuit is greater than about one hundred to one. The utility of these design parameters in instances where the ratio of capacitance is greater than a thousand to one, and the number of intermediate stages is ten or greater is particularly apparent.
In an integrated circuit structure wherein the output of a signal driver circuit contained on a monolithic chip is connected via multiple intermediate driver stages to the input of a load driving circuit, with the output capacitance of the load driver circuit being at least one hundred times greater than the output capacitance of the signal driver; a plurality of n intermediate driver stages which will minimize the total signal propogation delay between the signal driver and the load driver, where n is selected to be at least five and otherwise satisfies the equation n = 1n M with M = capacitance of load driver/capacitance of signal driver.
Claim 2
Dependent Claim
108 words
In an integrated circuit structure wherein the output of a signal driver circuit contained on a monolithic chip is connected via multiple intermediate driver stages to the input of a load driving circuit, with the output capacitance of the load driver circuit being at least one hundred times greater than the output capacitance of the signal driver; a plurality of n intermediate driver stages which will minimize the total signal propogation delay between the signal driver and the load driver, where n is selected to be at least five and otherwise satisfies the equation n = 1n M with M = capacitance of load driver/capacitance of signal driver.
Claim 3
Dependent Claim
42 words
The circuit of claim 1 wherein the capacitance of each intermediate stage is selected to be equal to the square root of the product of the output capacitance of the preceeding driver stage and the output capacitance of the succeeding driver stage.