Method for providing a semiconductor device with planarized contacts

Claim 2

A manufacturing method for providing a semiconductor device with an insulating layer having a generally planar surface and planar contacts according to the steps of: providing a semiconductor body having active areas with a patterned first electrically conductive layer having at least a portion protruding upward beyond adjacent parts of said conductive layer; forming a first electrically insulating layer on said first electrically conductive layer and on exposed adjacent parts of said semiconductor body in a manner such that a portion of said first insulating layer protrudes upwardly beyond adjacent parts of said first insulating layer generally at the location above the protruding portion of said first conductive layer; forming an additional layer having a generally planar upper surface on said first electrically insulating layer; exposing at least part of the protruding portion of said first electrically insulating layer by etching said additional layer with etchant that attacks the material of said additional layer at a significantly greater rate than the material of said first electrically insulating layer; etching the remainder of said additional layer and said first electrically insulating layer, as it becomes exposed, with etchant that etches the materials of said first electrically insulating layer and said additional layer at substantially equal rates thereby forming a generally planar upper surface on said first electrically insulating layer; forming at least one via to said first electrically conductive layer and at least one via to an active area of said semiconductor body by plasma etching through the remainder of said first insulating layer down to said first electrically conductive layer and to active areas of said semiconductor body; forming, on the upper surfce of said first insulating layer, a second conductive metal layer of a thickness sufficient to at least partially fill all said vias; at least one of said conductive layers being formed by vapor deposition; forming on said second conductive layer a planarizing layer having a generally planar upper surface; exposing at least part of said second conductive layer by etching said planarizing layer with etchant that attacks material of said planarizing layer at a significantly greater rate then material of said second conductive layer; and then etching said planarizing layer and said second conductive layer, as it becomes exposed, with etchant that attacks said second conductive layer and said planarizing layer at substantially equal rates until the upper surface of said first insulating layer is exposed.

Claim 3

The method of claim 1 wherein said first insulating layer comprises a silicon-dioxide containing material.

Claim 4

The method of claim 2 wherein said planarizing layer is an organic resist layer.

Claim 5

The method of claim 1 wherein each of said vias is formed by plasma etching with an anisotropic etch, the etch rate of which is significantly greater for said material of said first insulating layer than for the material of said first conductive layer.

Claim 6

The method of claim 2 wherein each of said vias is formed by plasma etching with an anisotropic etch, the etch rate of which is significantly greater for said material of said first insulating layer than for the material of said first conductive layer.

Claim 7

The method of claim 4 wherein said first insulating layer is a phospho-silicate glass.

Claim 8

The method of claim 1 wherein at least one of the conductive layers is formed by chemical vapor deposition.

Claim 9

The method of claim 7 wherein the first insulating layer comprises a semiconductor oxide.

Claim 10

The method of claim 7 wherein the second conductive layer is an electrically conducting polysilicon layer.

Claim 11

The method of claim 9 wherein the second conductive layer is formed by chemical vapor deposition.

Claim 12

The method of claim 7 wherein the second conductive layer is a metal layer.

Claim 13

The method of claim 1 wherein the second conductive layer is formed by chemical vapor deposition.

Claim 14

The method of claim 1 wherein the first conductive layer is a metal layer.

Claim 15

The method of claim 12 wherein the second conductive layer is a layer of a metal or a metal silicide selected from the group consisting of tungsten, aluminum, tungsten silicide, titanium silicide and mixtures thereof.

Claim 16

The method of claim 13 wherein the second conductive layer is a layer of a metal or a metal silicide selected from the group consisting of tungsten, aluminum, tungsten silicide, titanium silicide, and mixtures thereof.

Claim 17

The method of claim 4 wherein the etch rate of the anisotropic etch forming each of said vias is significantly greater for the material of said first insulating layer than for the material of said semiconductor body.

Claim 18

The method of claim 5 wherein the etch rate of the anisotropic etch forming each of said vias is significantly greater for the material of said first insulating layer than for the material of said semiconductor body.

Claim 19

A manufacturing method for providing a semiconductor device with an insulating layer having a generally planar surface and planar contacts according to the steps of: providing a semiconductor body having active areas with a patterned first electrically conductive layer having at least a portion protruding upward beyond adjacent parts of said conductive layer; forming a first electrically insulating layer comprising a semiconductor oxide on said first electrically conductive layer and on exposed adjacent parts of said semiconductor body in a manner such that a portion of said first insulating layer protrudes upwardly beyond adjacent parts of said first insulating layer generally at the location above the protruding portion of said first conductive layer; forming an additional layer having a generally planar upper surface on said first electrically insulating layer; exposing at least part of the protruding portion of said first electrically insulating layer by etching said additional layer with etchant that attacks the material of said additional layer at a significantly greater rate than the material of said first electrically insulating layer; etching the remainder of said additional layer and said first electrically insulating layer, as it becomes exposed, with etchant that etches the materials of said first electrically insulating layer and said additional layer at substantially equal rates thereby forming a generally planar upper surface on said first electrically insulating layer; forming at least one via to said first electrically conductive layer and at least one via to an active area of said semiconductor body by plasma etching through the remainder of said first insulating layer down to said first electrically conductive layer to active areas of said insulating layer; forming, on the upper surface of said first insulating layer, a second conductive layer of a thickness sufficient to at least partially fill all said vias; at least one of said conductive layers being formed by vapor deposition; forming on said second conductive layer a planarizing layer having a generally planar upper surface; exposing at least part of said second conductive layer by etching said planarizing layer with etchant that attacks material of said planarizing layer at a significantly greater rate than material of said second conductive layer; and then etching said planarizing layer and said second conductive layer, as it becomes exposed, with etchant that attacks said second conductive layer and said planarizing layer at substantially equal rates until the upper surface of said first insulating layer is exposed.

Claim 20

A manufacturing method for providing a semiconductor device with an insulating layer having a generally planar surface and planar contacts according to the steps of: providing a semiconductor body having active areas with a patterned first electrically conductive layer having at least a portion protruding upward beyond adjacent parts of said conductive layer; forming a first electrically insulating layer comprising a semiconductor oxide on said first electrically conductive layer and on exposed adjacent parts of said semiconductor body in a manner such that a portion of said first insulating layer protrudes upwardly beyond adjacent parts of said first insulating layer generally at the location above the protruding portion of said first conductive layer; forming an additional layer having a generally planar upper surface on said first electrically insulating layer; exposing at least part of the protruding portion of said first electrically insulating layer by etching said additional layer with etchant that attacks the material of said additional layer at a significantly greater rate than the material of said first electrically insulating layer; etching the remainder of said additional layer and said first electrically insulating layer, as it becomes exposed, with etchant that etches the materials of said first electrically insulating layer and said additional layer at substantially equal rates thereby forming a generally planar upper surface on said first electrically insulating layer; forming at least one via to said first electrically conductive layer and at least one via to an active area of said semiconductor body by plasma etching through the remainder of said first insulating layer down to said first electrically conductive layer to active areas of said insulating layer; forming, on the upper surface of said first insulating layer, a second conductive layer of a thickness sufficient to at least partially fill all said vias; at least one of said conductive layers being formed by vapor deposition; forming on said second conductive layer a planarizing layer having a generally planar upper surface; exposing at least part of said second conductive layer by etching said planarizing layer with etchant that attacks material of said planarizing layer at a significantly greater rate than material of said second conductive layer; and then etching said planarizing layer and said second conductive layer, as it becomes exposed, with etchant that attacks said second conductive layer and said planarizing layer at substantially equal rates until the upper surface of said first insulating layer is exposed.

Claim 21

The method of claim 18 wherein said first insulting layer comprises a silicon-dioxide containing material.

Claim 22

The method of claim 19 wherein said planarizing layer is an organic resist layer.

Claim 23

The method of claim 18 wherein each of said vias is formed by plasma etching with an anisotropic etch, the etch rate of which is significantly greater for said material of said first insulating layer than for the material of said first conductive layer.

Claim 24

The method of claim 19 wherein each of said vias is formed by plasma etching with an anisotropic etch, the etch rate of which is significantly greater for said material of said first insulating layer than for the material of said first conductive layer.

Claim 25

The method of claim 21 wherein the first insulating layer is a phospho-silicate glass.

Claim 26

The method of claim 18 wherein at least one of the conductive layers is formed by chemical vapor deposition.

Claim 27

The method of claim 24 wherein the first insulating layer comprises a semiconductor oxide.

Claim 28

The method of claim 18 wherein the first conductive layer is a metal layer, an electrically conductive polysilicon layer or a metal silicide layer.

Claim 29

The method of claim 26 wherein the second conductive layer is a layer of a metal selected from the group consisting of tungsten, aluminum, titanium and the metal silicides.

Claim 30

The method of claim 22 wherein the etch rate of the anisotropic etch forming each of said vias is significantly greater for the material of said first insulating layer than for the material of said semiconductor body.