Dynamic storage device with extended information holding time

Claim 2

A semiconductor memory circuit device comprising: a memory cell array formed at a predetermined area in a main surface of a semiconductor substrate, said memory cell array including a plurality of word lines arranged in parallel with each other in columns, a plurality of data lines arranged in parallel with each other in rows, and a plurality of 1-element type memory cells arrayed in rows and columns, each said memory cell comprising a capacitor which is made up of a semiconductor portion of said main surface of the semiconductor substrate serving as its one electrode and a conductive layer serving as its other electrode and formed on an insulating film formed over said portion of said semiconductor substrate and an insulated gate field-effect transistor electrically connected in series with said capacitor and having its gate electrode connected to one of said word lines, the series connection of said capacitor and insulated gate field-effect transistor being coupled to one of said data lines; and at least one semiconductor region having a conductivity type opposite to the conductivity type of said semiconductor substrate, extending substantially along and adjacently to said semiconductor portions of said capacitors of the memory cells arrayed at the most outside row or column of said memory cell array, and formed outside said predetermined area in said main surface of the semiconductor substrate along an edge of said predetermined area which is not opposite transistors in peripheral circuits of said semiconductor memory circuit, but not formed between said adjacent semiconductor portions of the capacitors arrayed at the adjacent rows or columns.

Claim 3

A semiconductor memory circuit device according to claim 1, wherein a junction between said semiconductor region and said semiconductor substrate is reverse-biased.

Claim 4

A semiconductor memory circuit device according to claim 2, wherein said semiconductor region is an impurity diffused region.

Claim 5

A semiconductor memory circuit device according to claim 1, wherein said predetermined area is defined in the form of a rectangle and said semiconductor region is formed along one side portion of said rectangular predetermined area.

Claim 6

A semiconductor memory circuit device according to claim 4, wherein said semicondcutor region extends in a direction traversing said data lines.

Claim 7

A semiconductor memory circuit device in accordance with claim 1, wherein said semiconductor region comprises a plurality of semiconductor regions extending substantially along and adjacently to said semiconductor portions of said capacitors of the memory cells arrayed at the most outside row or column of said memory cell array.

Claim 8

A semiconductor memory circuit device in accordance with claim 1, wherein said predetermined area has an irregularly-shaped boundary, and wherein said semiconductor region extending substantially along and adjacently to said semiconductor portions of said capacitors of the memory cells arrayed at the most outside row or column of said memory cell array conforms to said irregularly-shaped boundary.

Claim 9

A semiconductor memory circuit device in accordance with claim 1, wherein said semiconductor portion of said main surface of the semiconductor substrate is an impurity-doped region having a conductivity type opposite to the conductivity type of said semiconductor substrate.

Claim 10

A semiconductor memory circuit device in accordance with claim 1, wherein said semiconductor portion of said main surface of the semiconductor substrate is an inversion region.

Claim 11

A semiconductor memory circuit device comprising: a memory cell array formed at a predetermined area in a main surface of a semiconductor substrate, said memory cell array including a plurality of word lines arranged in parallel with each other in columns, a plurality of data lines arranged in parallel with each other in rows, and a plurality of 1- element type memory cells arrayed in rows and columns, each said memory cell comprising a capacitor which is made up of a semiconductor portion of said main surface of the semiconductor substrate serving as its one electrode and a conductive layer serving as its other electrode and formed on an insulating film formed over said portion of said semiconductor substrate and an insulated gate field-effect transistor electrically connected in series with said capacitor and having its gate electrode connected to one of said word lines, the series connection of said capacitor and insulated gate field-effect transistor being coupled to one of said data lines; and at least one inversion region extending substantially along and adjacently to said semiconductor portions of said capacitors of the memory cells arrayed at the most outside row or column of said memory cell array, and formed outside said predetermined area in said main surface of the semiconductor substrate, but not formed between said adjacent semiconductor portions of the capacitors arrayed at the adjacent rows or columns, wherein said inversion region is effected by a structure in which a conductive layer is formed on another insulating film formed over another semiconductor portion of said main surface where said inversion region is to be formed.

Claim 12

A semiconductor memory circuit device comprising: a memory cell array formed at a predetermined area in a main surface of a semiconductor substrate, said memory cell array including a plurality of word lines arranged in parallel with each other in columns, a plurality of data lines arranged in parallel with each other in rows, and a plurality of 1- element type memory cells arrayed in rows and columns, each said memory cell comprising a capacitor which is made up of a semiconductor portion of said main surface of the semiconductor substrate serving as its one electrode and a conductive layer serving as its other electrode and formed on an insulating film formed over said portion of said semiconductor substrate and an insulated gate field-effect transistor electrically connected in series with said capacitor and having its gate electrode connected to one of said word lines, the series connection of said capacitor and insulated gate field-effect transistor being coupled to one of said data lines; and at least one inversion region extending substantially along and adjacently to said semiconductor portions of said capacitors of the memory cells arrayed at the most outside row or column of said memory cell array, and formed outside said predetermined area in said main surface of the semiconductor substrate, but not formed between said adjacent semiconductor portions of the capacitors arrayed at the adjacent rows or columns, wherein said inversion region is effected by a structure in which a conductive layer is formed on another insulating film formed over another semiconductor portion of said main surface where said inversion region is to be formed.

Claim 13

A semiconductor memory circuit device according to claim 10, wherein said another insulating film is made of silicon oxide, and said conductive layer is made of polycrystalline silicon.

Claim 14

A semiconductor memory circuit device according to claim 11, wherein the junction between said inversion region and said semiconductor substrate is reverse-biased.

Claim 15

A semiconductor memory circuit device according to claim 12, wherein said predetermined area is defined in the form of a rectangle and said inversion region is formed along one side portion of said rectangular predetermined area.

Claim 16

A semiconductor memory circuit device comprising: a memory cell array formed at a predetermined area in a main surface of a semiconductor substrate, said memory cell array including a plurality of word lines arranged in parallel with each other in columns, a plurality of data lines arranged in parallel with each other in rows, and a plurality of 1-element type memory cells arrayed in rows and columns, each said memory cell comprising a capacitor which is made up of a semiconductor portion of said main surface of the semiconductor substrate serving as its one electrode and a conductive layer sreving as its other electrode and formed on an insulating film formed over said portion of said semiconductor substrate and an insulated gate field-effect transistor electrically connected in series with said capacitor and having its gate electrode connected to one of said word lines, the series connection of said capacitor and insulated gate field-effect transistor being coupled to one of said data lines; and at least one semiconductor region having a conductivity type opposite to the conductivity type of said semiconductor substrate, extending substantially along and adjacently to said semiconductor portions of said capacitors of the memory cells arrayed at the most outside row or column of said memory cell array and formed outside said predetermined area in said main surface of the semiconductor substrate, but not formed between said adjacent semiconductor portions of the capacitors arrayed at the adjacent rows or columns, wherein said predetermined area has an irregularly-shaped boundary, and wherein said semiconductor region extending substantially along and adjacently to said semiconductor portions of said capacitors of the memory cells arrayed at the most outside row or column of said memory cell array conforms to said irregularly-shaped boundary.

Claim 17

A semiconductor memory circuit device comprising: a memory cell array formed at a predetermined area in a main surface of a semiconductor substrate, said memory cell array including a plurality of word lines arranged in parallel with each other in columns, a plurality of data lines arranged in parallel with each other in rows, and a plurality of 1-element type memory cells arrayed in rows and columns, each said memory cell comprising a capacitor which is made up of a semiconductor portion of said main surface of the semiconductor substrate serving as its one electrode and a conductive layer sreving as its other electrode and formed on an insulating film formed over said portion of said semiconductor substrate and an insulated gate field-effect transistor electrically connected in series with said capacitor and having its gate electrode connected to one of said word lines, the series connection of said capacitor and insulated gate field-effect transistor being coupled to one of said data lines; and at least one semiconductor region having a conductivity type opposite to the conductivity type of said semiconductor substrate, extending substantially along and adjacently to said semiconductor portions of said capacitors of the memory cells arrayed at the most outside row or column of said memory cell array and formed outside said predetermined area in said main surface of the semiconductor substrate, but not formed between said adjacent semiconductor portions of the capacitors arrayed at the adjacent rows or columns, wherein said predetermined area has an irregularly-shaped boundary, and wherein said semiconductor region extending substantially along and adjacently to said semiconductor portions of said capacitors of the memory cells arrayed at the most outside row or column of said memory cell array conforms to said irregularly-shaped boundary.

Claim 18

A semiconductor memory circuit device in accordance with claim 14, wherein said semiconductor region comprises a plurality of semiconductor regions extending substantially along and adjacently to said semiconductor portions of said capacitors of the memory cells arrayed at the most outside row or column of said memory cell array.

Claim 19

A semiconductor memory circuit device in accordance with claim 14, wherein said semiconductor portion of said main surface of the semiconductor substrate is an impurity-doped region having a conductivity type opposite to the conductivity type of said semiconductor substrate.

Claim 20

A semiconductor memory circuit device in accordance with claim 14, wherein said semiconductor portion of said main surface of the semiconductor substrate is an inversion region.