Semiconductor memory

Claim 2

A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; a differential amplifier to which signals on said pair of data line portions are respectively applied; and means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions.

Claim 3

A semiconductor memory according to claim 1, further comprising, a pair of second word lines orthogonally crossing over said data line portions; a first dummy memory cell coupled to one of the data line portions of said pair of data line portions and one of said second word lines at the cross point thereof, and a second dummy memory cell coupled to the other of the data line portions of said pair of data line portions and the other of said second word lines at the cross point thereof.

Claim 4

A semiconductor memory according to claim 1, wherein said output signal deriving means comprises a pair of switching elements connected to said data line portions and a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively applied through said pair of switching elements

Claim 5

A semiconductor memory according to claim 3, wherein said switching elements comprise a pair of transistors, each having an input terminal connected to a respective data line portion, an output terminal connected to said second differential amplifier, and a control terminal to which a control signal is applied.

Claim 6

A semiconductor memory according to claim 1, wherein each of said memory cells comprises a metal-oxide-semiconductor transistor and a storage capacitor connected therewith.

Claim 7

A semiconductor memory according to claim 1, wherein, for each of said data line portions, the memory cells coupled thereto are coupled, alternately, to every other word line.

Claim 8

A semiconductor memory according to claim 1, wherein, for each of said data line portions, the memory cells coupled thereto are coupled in alternate pairs of adjacent word lines.

Claim 9

A semiconductor memory according to claim 1, wherein for each of said data line portions, the memory cells coupled thereto are coupled in alternate groups of four of adjacent word lines.

Claim 10

A semiconductor memory according to claim 1, wherein said memory cells are coupled to said data line portions and said word lines so that the electrical characteristics of said data line portions are balanced with respect to each other.

Claim 11

A semiconductor memory according to claim 1, wherein the number of memory cells connected to one of the data line portions of said pair of data line portions is equal to the number of memory cells connected to the other of the data line portions of said pair of data line portions.

Claim 12

A semiconductor memory according to claim 3, further comprising a pair of second word lines orthogonally crossing over said data line portions; a first dummy memory cell coupled to one of the data line portions of said pair of data line portions and one of said second word lines at the cross point thereof; and a second dummy memory cell coupled to the other of the data line portions of said pair of data line portions and the other of said second word lines at the cross point thereof.

Claim 13

A semiconductor memory according to claim 11, wherein said switching elements comprise a pair of transistors, each having an input terminal connected to a respective data line portion, an output terminal connected to said second differential amplifier, and a control terminal to which a control signal is applied.

Claim 14

A semiconductor memory according to claim 1, wherein said data line portions are formed of aluminum and said first word lines are formed of polysilicon.

Claim 15

A random access semiconductor memory comprising: first and second data line portions disposed parallel and adjacent to each other a plurality of first word lines orthogonally crossing over each of said data line portions; a plurality of memory cells, disposed at the cross points of said first word lines and one of said data line portions, each of which memory cells is capable of storing selected information to be written therein and is capable of reading out information stored therein, each memory cell having an address terminal connected to a respective word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to one of said data line portions; a differential amplifier connected to each of said data line portions for differentially amplifying signals supplied thereby; means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions; a pair of second word lines orthogonally crossing over each of said data line portions; a first dummy memory cell, disposed at the crosspoint of one of said second word lines and said first data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said one of said second word lines, and having a data terminal connected to said first data line portion; and a second dummy memory cell, disposed at the crosspoint of the other of said second word lines and said second data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said other of said second word lines, and having a data terminal connected to said second data line portion.

Claim 16

A random access semiconductor memory comprising: first and second data line portions disposed parallel and adjacent to each other a plurality of first word lines orthogonally crossing over each of said data line portions; a plurality of memory cells, disposed at the cross points of said first word lines and one of said data line portions, each of which memory cells is capable of storing selected information to be written therein and is capable of reading out information stored therein, each memory cell having an address terminal connected to a respective word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to one of said data line portions; a differential amplifier connected to each of said data line portions for differentially amplifying signals supplied thereby; means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions; a pair of second word lines orthogonally crossing over each of said data line portions; a first dummy memory cell, disposed at the crosspoint of one of said second word lines and said first data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said one of said second word lines, and having a data terminal connected to said first data line portion; and a second dummy memory cell, disposed at the crosspoint of the other of said second word lines and said second data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said other of said second word lines, and having a data terminal connected to said second data line portion.

Claim 17

A random access semiconductor memory according to claim 14, wherein said output signal deriving means comprises a pair of switching elements connected to said data line portions and a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively applied through said pair of switching elements.

Claim 18

A semiconductor memory according to claim 15, wherein each of said memory cells comprises a metal-oxide-semiconductor transistor and a storage capacitor connected therewith.

Claim 19

A semiconductor memory according to claim 16, wherein said switching elements comprise a pair of transistors, each having an input terminal connected to a respective data line portion, an output terminal connected to said second differential amplifier, and a control terminal to which a control signal is applied.