US3879640A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Protective diode network for MOS devices
Assignee: RCA Corp
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Filing: 1974-02-11
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Granted: 1975-04-22
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Expires: 1994-02-11
Abstract
Abstract A protective diode network for a differential amplifier comprised of insulated gate field effect transistors. The network provides for both gate-to-gate and gate-to-source protection using a small number of components with minimal capacitive and leakage loading.
Inventors
- 👤 Jr Otto Heinrich Schade
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 00:45
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F1/00; H03F1/52; H03F1/523; H10; H10D; H10D84/00; H10D84/80; H10D84/811; H10D89/00; H10D89/60; H10D89/601; H10D89/611
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
224 words
The combination comprising: a substrate of semiconductor material of first conductivity type; a layer of semiconductor material of second conductivity type disposed on said substrate and forming a first PN junction therewith; first and second field effect transistors, each comprising first and second spaced apart regions of first conductivity type, defining the source and drain regions, respectively, disposed in said layer at a surface thereof, and a gate electrode overlying said surface between said first and second regions; means connecting said transistors in a differential configuration including means connecting the source regions of said first and second transistors to a common point; means protecting said first and second transistors against overvoltages applied between the gates of said transistors and between the gates and the sources of said transistors comprising: an additional region of first conductivity type disposed within said layer and forming a second PN junction therewith; three spaced apart regions of second conductivity type disposed within said additional region, each of said three spaced apart regions forming a PN junction with said additional region; and means electrically connecting the gate electrode of said first transistor to one of said three regions, means electrically connecting the gate electrode of said second transistor to a second one of said three regions, and means connecting the third one of said three regions to said common point.
Claim 2
Dependent Claim
224 words
The combination comprising: a substrate of semiconductor material of first conductivity type; a layer of semiconductor material of second conductivity type disposed on said substrate and forming a first PN junction therewith; first and second field effect transistors, each comprising first and second spaced apart regions of first conductivity type, defining the source and drain regions, respectively, disposed in said layer at a surface thereof, and a gate electrode overlying said surface between said first and second regions; means connecting said transistors in a differential configuration including means connecting the source regions of said first and second transistors to a common point; means protecting said first and second transistors against overvoltages applied between the gates of said transistors and between the gates and the sources of said transistors comprising: an additional region of first conductivity type disposed within said layer and forming a second PN junction therewith; three spaced apart regions of second conductivity type disposed within said additional region, each of said three spaced apart regions forming a PN junction with said additional region; and means electrically connecting the gate electrode of said first transistor to one of said three regions, means electrically connecting the gate electrode of said second transistor to a second one of said three regions, and means connecting the third one of said three regions to said common point.
Claim 3
Dependent Claim
224 words
The combination comprising: a substrate of semiconductor material of first conductivity type; a layer of semiconductor material of second conductivity type disposed on said substrate and forming a first PN junction therewith; first and second field effect transistors, each comprising first and second spaced apart regions of first conductivity type, defining the source and drain regions, respectively, disposed in said layer at a surface thereof, and a gate electrode overlying said surface between said first and second regions; means connecting said transistors in a differential configuration including means connecting the source regions of said first and second transistors to a common point; means protecting said first and second transistors against overvoltages applied between the gates of said transistors and between the gates and the sources of said transistors comprising: an additional region of first conductivity type disposed within said layer and forming a second PN junction therewith; three spaced apart regions of second conductivity type disposed within said additional region, each of said three spaced apart regions forming a PN junction with said additional region; and means electrically connecting the gate electrode of said first transistor to one of said three regions, means electrically connecting the gate electrode of said second transistor to a second one of said three regions, and means connecting the third one of said three regions to said common point.
Claim 4
Dependent Claim
224 words
The combination comprising: a substrate of semiconductor material of first conductivity type; a layer of semiconductor material of second conductivity type disposed on said substrate and forming a first PN junction therewith; first and second field effect transistors, each comprising first and second spaced apart regions of first conductivity type, defining the source and drain regions, respectively, disposed in said layer at a surface thereof, and a gate electrode overlying said surface between said first and second regions; means connecting said transistors in a differential configuration including means connecting the source regions of said first and second transistors to a common point; means protecting said first and second transistors against overvoltages applied between the gates of said transistors and between the gates and the sources of said transistors comprising: an additional region of first conductivity type disposed within said layer and forming a second PN junction therewith; three spaced apart regions of second conductivity type disposed within said additional region, each of said three spaced apart regions forming a PN junction with said additional region; and means electrically connecting the gate electrode of said first transistor to one of said three regions, means electrically connecting the gate electrode of said second transistor to a second one of said three regions, and means connecting the third one of said three regions to said common point.
Claim 5
Dependent Claim
41 words
The combination as claimed in claim 1 wherein said means connecting said transistors in a differential configuration includes an impedance means connected at one end to the source regions of said transistors and at its other end to a first terminal.
Claim 6
Dependent Claim
34 words
The combination as claimed in claim 2 wherein said means connecting said transistors in a differential configuration includes impedance means connected between the drain region of one of said transistors and a second terminal.
Claim 7
Dependent Claim
50 words
The combination as claimed in claim 3 further including means for applying the same potential to said second terminal and to said substrate and including means for applying a potential between said first and second terminals having a polarity to reverse bias the PN junctions formed by said three regions.
Claim 8
Dependent Claim
46 words
The combination as claimed in claim 1 wherein said additional region is isolated from said first and second transistors, and wherein said first and second transistors are connected at their sources to that portion of said layer in which their source and drain regions are disposed.
Claim 9
Dependent Claim
42 words
The combination as claimed in claim 1, furtheR including means for applying a potential between said substrate and the sources of said transistors having a polarity to reverse bias said first PN junction and the PN junctions formed by said three regions.
Claim 10
Dependent Claim
138 words
The combination comprising: first and second insulated-gate field-effect transistors, each transistor having a gate, a source and a drain; means connecting the sources of said transistors to a first node; a first terminal for the application thereto of an operating potential; impedance means connected between said first node and said first terminal; first and second input terminals connected to the gates of said first and second transistors, respectively; first, second and third diodes, each diode having an anode region and a cathode region; the same one of said anode and cathode regions of said three diodes being connected in common; and the other one of said anode and cathode region of said first, second and third diodes being connected to the gate of said first transistor, the gate of said second tansistor and to said first node, respectively.
Claim 11
Dependent Claim
138 words
The combination comprising: first and second insulated-gate field-effect transistors, each transistor having a gate, a source and a drain; means connecting the sources of said transistors to a first node; a first terminal for the application thereto of an operating potential; impedance means connected between said first node and said first terminal; first and second input terminals connected to the gates of said first and second transistors, respectively; first, second and third diodes, each diode having an anode region and a cathode region; the same one of said anode and cathode regions of said three diodes being connected in common; and the other one of said anode and cathode region of said first, second and third diodes being connected to the gate of said first transistor, the gate of said second tansistor and to said first node, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-21 | 1978-10-21 | 1979-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-21 | 1982-10-21 | 1983-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-21 | 1986-10-21 | 1987-04-22 | $7700.00 | Window Closed / Lapsed |