MOSFET process using implantation through silicon

Claim 2

In a process for forming a MOS integrated circuit on a substrate having device active regions, the sequence comprising: forming a silicon layer which is approximately 150-200 nanometers thick over the device active regions; forming a mask over the silicon defining first edge boundaries of first source and drain regions; subjecting the structure to a relatively high energy implant dose for penetrating the silicon layer to form one of an n + or a p + implant in the surface-adjacent substrate region of the first source and drain region at the first edge boundary; etching the silicon layer in the presence of the mask to pattern the silicon to a gate electrode of selected lateral dimensions recessed a predetermined dimension beneath the first edge boundaries of the mask; removing the mask; subjecting the structure to a relatively low energy implant of the same conductivity type as the high energy implant to form lightly doped regions self-aligned with the first source and drain regions and the gate electrode; and applying a thermal cycle to activate the implanted species and drive-in the implanted species.

Claim 3

The process of claim 1, having the additional step of forming a conductive shunt layer on the silicon.

Claim 4

The process of claim 2, wherein following the low energy implant the structure is subjected to a second low energy opposite conductivity implant to form guard band doped regions about the lightly doped regions.

Claim 5

The process of claim 3, wherein after the thermal cycle a conformal layer of silicon dioxide is deposited on the structure and subjected to an anisotropic etch to remove horizontal sections of the layer and thereby provide gate sidewall oxide spacers.

Claim 6

In a process for forming a MOS integrated circuit on a substrate having device active regions, the sequence comprising: forming a silicon layer which is approximately 150-200 nanometers thick over the device active regions; forming a mask on the upper surface of the silicon comprising a layer of photoresist over a layer of silicon nitride to define first edge boundaries of source and drain regions; subjecting the structure to a relatively high energy implant dose for penetrating the silicon layer to form one of an n + or a p + implant in the surface-adjacent substrate region of the first source and drain region at the first edge boundary; etching the silicon layer in the presence of the mask to pattern the silicon to a gate electrode recessed a predetermined dimension beneath the first edge boundaries of the mask; removing the photoresist portion of the mask; subjecting the structure to a relatively low energy implant of the same conductivity type as the high energy implant to form lightly doped regions self-aligned with and between the source and drain regions and the gate electrode; applying a thermal oxidation cycle to selectively oxidize the unmasked sidewalls of the silicon gate electrode but not the nitride-protected upper surface of the silicon; removing the silicon nitride portion of the mask; and forming a conductive shunt layer on the silicon.

Claim 7

In a process for forming a MOS integrated circuit on a substrate having device active regions, the sequence comprising: forming a silicon layer which is approximately 150-200 nanometers thick over the device active regions; forming a mask on the upper surface of the silicon comprising a layer of photoresist over a layer of silicon nitride to define first edge boundaries of source and drain regions; subjecting the structure to a relatively high energy implant dose for penetrating the silicon layer to form one of an n + or a p + implant in the surface-adjacent substrate region of the first source and drain region at the first edge boundary; etching the silicon layer in the presence of the mask to pattern the silicon to a gate electrode recessed a predetermined dimension beneath the first edge boundaries of the mask; removing the photoresist portion of the mask; subjecting the structure to a relatively low energy implant of the same conductivity type as the high energy implant to form lightly doped regions self-aligned with and between the source and drain regions and the gate electrode; applying a thermal oxidation cycle to selectively oxidize the unmasked sidewalls of the silicon gate electrode but not the nitride-protected upper surface of the silicon; removing the silicon nitride portion of the mask; and forming a conductive shunt layer on the silicon.

Claim 8

The process of claim 5, wherein following the low energy implant the structure is subjected to a second low energy opposite conductivity implant to form guard band regions about the lightly doped regions.