Digital multiplication circuit for use in a microprocessor

Claim 1

A digital multiplication circuit comprising: a Booth recoder means for recoding a multiplier into N Booth operation sets where N is a positive integer that equals one half the number of bits in the multiplier; a plurality of N partial product selector means having inputs and outputs connected in cascade arrangement from output to input with the Nth output being an intermediate output of the digital multiplication circuit, the cascade arrangement being N multiplicand sets of M bits in length and each member of the plurality of N partial product selector means being connected to a member of the N operation sets for implementing the recoded Booth operation set on a multiplicand set and where M is a positive integer; summation means for summing the contents of the plurality of N partial product selector means the summation means including a second plurality of summing means with predetermined members of the second plurality of summing means being located between predetermined members of the plurality of N partial product selector means; and a domino means, operatively connected to the plurality of partial product selector means, for generating a plurality of evaluation pulses with each single evaluation pulse of the plurality of evaluation pulses being generated to represented a worse case signal propagation time delay through a predetermined partial product selector means and connected to evaluate the predetermined member of the plurality of partial product selector means to provide outputs therefrom of each single partial product selector means when evaluated.

Claim 14

A method of performing digital multiplication comprising: decoding a multiplier into N Booth operation sets where N is a positive integer that equals one half the number of bits in the multiplier; implementing a decoded Booth operation set on a multiplicand sets of M bits in length with a plurality of N partial product selector means having inputs and outputs connected in cascade arrangement from output to input with the nth output being an intermediate output of the the multiplication and each member of the plurality of N partial product selector means being connected to receive a member of the N Booth operation sets; summing the contents of the plurality of N partial product selector means with a summation means including a second plurality of summing means with predetermined members of the second plurality of summing means being located between predetermined members of the plurality of N partial product registers; and generating a plurality of evaluation pulses with each single evaluation pulse being generated to represent a worse case single propagation time delay through a predetermined partial product selector means of the plurality of partial product selector means and connected to evaluate the predetermined member of the plurality of partial product selector means to provide an output thereby.

Claim 15

A method of performing digital multiplication comprising: decoding a multiplier into N Booth operation sets where N is a positive integer that equals one half the number of bits in the multiplier; implementing a decoded Booth operation set on a multiplicand sets of M bits in length with a plurality of N partial product selector means having inputs and outputs connected in cascade arrangement from output to input with the nth output being an intermediate output of the the multiplication and each member of the plurality of N partial product selector means being connected to receive a member of the N Booth operation sets; summing the contents of the plurality of N partial product selector means with a summation means including a second plurality of summing means with predetermined members of the second plurality of summing means being located between predetermined members of the plurality of N partial product registers; and generating a plurality of evaluation pulses with each single evaluation pulse being generated to represent a worse case single propagation time delay through a predetermined partial product selector means of the plurality of partial product selector means and connected to evaluate the predetermined member of the plurality of partial product selector means to provide an output thereby.