US4642883A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor bipolar integrated circuit device and method for fabrication thereof
Assignee: Fujitsu Ltd
•
Filing: 1985-01-28
•
Granted: 1987-02-17
•
Expires: 2005-01-28
Abstract
Abstract Disclosed is a structure of a semiconductor integrated circuit device including circuit elements such as a bipolar transistor and I 2 L. The structure comprises a buried layer formed by the ion implantation method using an insulating layer, having a window with tapered edges at the surface of semiconductor substrate, as a mask. A part of the buried layer appears at the surface of the semiconductor substrate, thus establishing the connection of electrodes. The circuit element is formed in the region bounded by the buried layer and the window.
Inventors
- 👤 Junji Sakurai
- 👤 Hajime Kamioka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:05
CPC Classifications
H; H10; H10W; H10W15/00; H10P; H10P30/00; H10P30/20; H10P30/22; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10W15/01; H10P90/1908; H10W10/011; H10W10/012; H10W10/13; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/023; Y10S148/087
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
153 words
A method for fabricating a bipolar semiconductor integrated circuit device comprising the steps of: (a) forming an insulating layer on a semiconductor substrate; (b) defining an active region of said semiconductor substrate by the window; (c) ion implanting impurities into the semiconductor substrate using the insulating layer as a mask; (d) forming buried ion implanted layer in the area not masked by the insulating layer, the buried layer extending up to the surface of the semiconductor substrate at the tapered edges of the insulating layer and extends continuously into the insulating layer from the surface of the semiconductor substrate; (e) exposing at least a part of the ion implanted layer at the surface of the semiconductor substrate by removing a portion of the insulating layer; and (f) forming a circuit element having the ion implanted layer as the buried layer, in a region of the semiconductor substrate surrounded by the ion implanted layer.
Claim 2
Independent Claim
153 words
A method for fabricating a bipolar semiconductor integrated circuit device comprising the steps of: (a) forming an insulating layer on a semiconductor substrate; (b) defining an active region of said semiconductor substrate by the window; (c) ion implanting impurities into the semiconductor substrate using the insulating layer as a mask; (d) forming buried ion implanted layer in the area not masked by the insulating layer, the buried layer extending up to the surface of the semiconductor substrate at the tapered edges of the insulating layer and extends continuously into the insulating layer from the surface of the semiconductor substrate; (e) exposing at least a part of the ion implanted layer at the surface of the semiconductor substrate by removing a portion of the insulating layer; and (f) forming a circuit element having the ion implanted layer as the buried layer, in a region of the semiconductor substrate surrounded by the ion implanted layer.
Claim 3
Dependent Claim
46 words
A method for fabricating a bipolar semiconductor integrated circuit device according to claim 1, wherein (d), comprises forming said buried ion implanted layer at a depth ranging from 5,000-6,000 Å within the silicon substrate, and at a depth ranging from 4,000-4,5000 Å in said insulating layer.
Claim 4
Dependent Claim
40 words
A method for fabricating a bipolar semiconductor integrated circuit according to claim 1, wherein in step (c) comprises performing said ion implanting with an acceleration energy of approximately 400 KeV and a dose of approximately 1×10 15 atoms/cm 2 .
References Cited (Backward Citations)
US3814995A
Cited
US3974560A
Cited
US4056413A
Cited
US4089021A
Cited
JPS5387672A
Cited
US4223328A
Cited
US4219369A
Cited
DE2845062A1
Cited
US4382826A
Cited
US4454524A
Cited
JPS54151377A
Cited
JPS54152981A
Cited
US4199776A
Cited
US4277882A
Cited
US4261761A
Cited
US4261763A
Cited
US4298402A
Cited
US4390890A
Cited
US4445266A
Cited
US4598462A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-16 | 1990-08-18 | 1991-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-16 | 1994-08-18 | 1995-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-16 | 1998-08-18 | 1999-02-17 | $7700.00 | Window Closed / Lapsed |