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US4390890A Expired / Lapsed US ⏱️ 0.0 years remaining

Saturation-limited bipolar transistor device

Assignee: International Business Machines Corp
•
Filing: 1980-06-26
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Granted: 1983-06-28
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Expires: 2000-06-26
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Abstract

Abstract A saturation-limited bipolar transistor device or circuit and a method of making same are provided which includes a merged NPN transistor and a PNP transistor structure formed so as to produce denser cells or circuits. A simple process is used to form the structure which includes a double diffused technique for making the PNP transistor. The PNP transistor has a double diffused emitter-base arrangement wherein the emitter is asymmetrically positioned with respect to the base so as to also serve as a contact for the base of the NPN transistor. The PNP transistor limits the input current by bypassing excess current to a silicon semiconductor substrate or chip. The structure includes an N type epitaxial layer formed on an N type subcollector with a P type region provided near the surface of the epitaxial layer. The epitaxial layer serves as the NPN collector and as the PNP base contact region. A first N type region is formed through the P type region extending from the surface of the epitaxial layer to the subcollector dividing the P type region into first and second sections which serve as the PNP collector region and the NPN base region, respectively. A second N type region is formed in the second section of the P type region at the surface of the epitaxial layer acting as the NPN emitter and a P+ region is formed in the first N type region at the surface of the epitaxial layer extending into the second section of the P type region which forms the NPN transistor base. This P+ region serves as the PNP emitter and as the NPN base contact.

Inventors

  • 👤 David L. Bergeron
  • 👤 Parsotam T. Patel

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 22:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/02; H03K19/08; H03K19/082; H03K19/088; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/0116; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/611; H10D84/613; H10D84/615; H10D84/63

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 216 words
A semiconductor structure comprising; a semiconductor substrate having a first N type region, a first P type region having first and second sections disposed between said first N type region and a surface of said substrate, a second N type region disposed between said first and second P type sections, extending from said surface to said first N type region and having a given maximum dopant concentration, a third N type region disposed between the second section of said first P type region and said first N type region having a maximum dopant concentration lower than that of said second N type region, a fourth N type region formed within the second section of said P type region at said surface and a second P type region having a maximum dopant concentration substantially higher than the maximum dopant concentration in said first P type region and disposed at said surface within said substrate in contact with said second N type region and said second section, first contact means connected to said second N type region through said first N type region, second contact means connected to said fourth N type region, third contact means connected to the first section of said first P type region, and fourth contact means connected to said second P type region.
Claim 2
Dependent Claim 216 words
A semiconductor structure comprising; a semiconductor substrate having a first N type region, a first P type region having first and second sections disposed between said first N type region and a surface of said substrate, a second N type region disposed between said first and second P type sections, extending from said surface to said first N type region and having a given maximum dopant concentration, a third N type region disposed between the second section of said first P type region and said first N type region having a maximum dopant concentration lower than that of said second N type region, a fourth N type region formed within the second section of said P type region at said surface and a second P type region having a maximum dopant concentration substantially higher than the maximum dopant concentration in said first P type region and disposed at said surface within said substrate in contact with said second N type region and said second section, first contact means connected to said second N type region through said first N type region, second contact means connected to said fourth N type region, third contact means connected to the first section of said first P type region, and fourth contact means connected to said second P type region.
Claim 3
Dependent Claim 26 words
A semiconductor structure as set forth in claim 1 wherein said fourth contact means is a doped polysilicon segment disposed on the surface of said substrate.
Claim 4
Dependent Claim 28 words
A semiconductor structure as set forth in claim 2 wherein said first N type region is a buried subcollector and said third contact means is an isolation region.
Claim 5
Dependent Claim 59 words
A semiconductor structure as set forth in claim 1 wherein the second section of said first P type region has a maximum dopant concentration of approximately between 1×10 16 and 5×10 17 boron atoms per cubic centimeter and said second P type region has a maximum dopant concentration between 1×10 19 and 3×10 20 boron atoms per cubic centimeter.

References Cited (Backward Citations)

UST957007I4 Cited
US4027180A Cited
US4110126A Cited
US4190466A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-06-27 1986-12-27 1987-06-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-06-27 1990-12-27 1991-06-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-06-27 1994-12-27 1995-06-28 $7700.00 Window Closed / Lapsed

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