Integrated circuit transistor arrangement having a low charge storage period

Claim 2

A transistor arrangement having a relatively low charge storage period comprising, a semiconductor substrate of P type conductivity having an electrically conductive layer formed on one of the major surfaces thereof and a semiconductive layer of N type conductivity formed on the other major surface thereof; a first N+ type region situated at the interface of the substrate and the N type layer; a second N+ type region formed in the surface of the N type layer and extending to the first region; a P type region formed in the surface of the N type layer, the first region being partially overlapped by the P type region; two spaced-apart P+ type regions formed in the surface of the N type layer, each of the P+ type regions being contiguous with and situated at opposite sides of, the P type region; a third N+ type region formed in the surface of the P type region; electrical contacts for the second, third, and each of the P+ type regions; and a protective oxide layer formed on the exposed regions of the surface of the N type layer.

Claim 3

A transistor arrangement as claimed in claim 1 wherein the semiconductor substrate is common to a plurality of said transistor arrangements and wherein the N type layer is divided into a number of sections by P+ type regions which extend from the surface of the N type layer to the interface of the N type layer with the substrate, each of the divided sections comprising a separate transistor arrangement.

Claim 4

A transistor arrangement having a relatively low charge storage period including an N.P.N. transistor having the base thereof connected to the emitter of a P.N.P. transistor and to an input terminal, the collector thereof connected to the base of the P.N.P. transistor and to an electrical supply terminal, and the emitter thereof connected to the collector of the P.N.P. transistor and to another electrical supply terminal, the transistor arrangement in the form of an integrated circuit which includes a semiconductor substrate of P type conductivity having an electrically conductive layer formed on one of the major surfaces thereof and a semiconductive layer of N type conductivity formed on the other major surface thereof; a first N+ type region situated at the interface of the substrate and the N type layer; a second N+ type region formed in the surface of the N type layer and extending to the first region; a P type region formed in the surface of the N type layer, the first region being partially overlapped by the P type region; two spaced-apart P+ type regions formed in the surface of the N type layer, each of the P+ type regions being contiguous with and situated at opposite sides of, the P type region; a third N+ type region formed in the surface of the P type region; electrical contacts for the second, third, and each of the P+ type regions; and a protective oxide layer formed on the exposed regions of the surface of the N type layer.

Claim 5

A transistor arrangement having a relatively low charge storage period including an N.P.N. transistor having the base thereof connected to the emitter of a P.N.P. transistor and to an input terminal, the collector thereof connected to the base of the P.N.P. transistor and to an electrical supply terminal, and the emitter thereof connected to the collector of the P.N.P. transistor and to another electrical supply terminal, the transistor arrangement in the form of an integrated circuit which includes a semiconductor substrate of P type conductivity having an electrically conductive layer formed on one of the major surfaces thereof and a semiconductive layer of N type conductivity formed on the other major surface thereof; a first N+ type region situated at the interface of the substrate and the N type layer; a second N+ type region formed in the surface of the N type layer and extending to the first region; a P type region formed in the surface of the N type layer, the first region being partially overlapped by the P type region; two spaced-apart P+ type regions formed in the surface of the N type layer, each of the P+ type regions being contiguous with and situated at opposite sides of, the P type region; a third N+ type region formed in the surface of the P type region; electrical contacts for the second, third, and each of the P+ type regions; and a protective oxide layer formed on the exposed regions of the surface of the N type layer.

Claim 6

A transistor arrangement capable of use in a saturated mode logic array having a relatively low charge storage period including an N.P.N. transistor having the base thereof connected to the emitter of a P.N.P. transistor and to an input terminal, the collector thereof connected to the base of the P.N.P. transistor and to an electrical supply terminal, and the emitter thereof connected to the collector of the P.N.P. transistor and to another electrical supply terminal, the transistor arrangement in the form of an integrated circuit which includes a semiconductor substrate of P type conductivity having an electrically conductive layer formed on one of the major surfaces thereof and a semiconductive layer of N type conductivity formed on the other major surface thereof; a first N+ type region situated at the interface of the substrate and the N type layer; a second N+ type region formed in the surface of the N type layer and extending to the first region; a P type region formed in the surface of the N type layer, the first region being partially overlapped by the P type region; two spaced-apart P+ regions formed in the surface of the N type layer, each of the P+ type regions being contiquous with and situated at opposite sides of, the P type region; a third N+ type region formed in the surface of the P type region; electrical contacts for the second, third, and each of the P+ type regions; and a protective oxide layer formed on the exposed regions of the surface of the N type layer.

Claim 7

A transistor arrangement capable of use in a saturated mode logic array having a relatively low charge storage period including an N.P.N. transistor having the base thereof connected to the emitter of a P.N.P. transistor and to an input terminal, the collector thereof connected to the base of the P.N.P. transistor and to an electrical supply terminal, and the emitter thereof connected to the collector of the P.N.P. transistor and to another electrical supply terminal, the transistor arrangement in the form of an integrated circuit which includes a semiconductor substrate of P type conductivity having an electrically conductive layer formed on one of the major surfaces thereof and a semiconductive layer of N type conductivity formed on the other major surface thereof; a first N+ type region situated at the interface of the substrate and the N type layer; a second N+ type region formed in the surface of the N type layer and extending to the first region; a P type region formed in the surface of the N type layer, the first region being partially overlapped by the P type region; two spaced-apart P+ regions formed in the surface of the N type layer, each of the P+ type regions being contiquous with and situated at opposite sides of, the P type region; a third N+ type region formed in the surface of the P type region; electrical contacts for the second, third, and each of the P+ type regions; and a protective oxide layer formed on the exposed regions of the surface of the N type layer.

Claim 8

A transistor arrangement capable of use in a saturated mode logic array in a programmable logic array having a relatively low charge storage period including an N.P.N. transistor having the base thereof connected to the emitter of a P.N.P. transistor and to an input terminal, the collector thereof connected to the base of the P.N.P. transistor and to an electrical supply terminal, and the emitter thereof connected to the collector of the P.N.P. transistor and to another electrical supply terminal, the transistor arrangement in the form of an integrated circuit which includes a semiconductor substrate of P type conductivity having an electrically conductive layer formed on one of the major surfaces thereof and a semiconductive layer of N type conductivity formed on the other major surface thereof; a first N+ type region situated at the interface of the substrate and the N type layer; a second N+ type region formed in the surface of the N type layer and extending to the first region; a P type region formed in the surface of the N type layer, the first region being partially overlapped by the P type region; two spaced-apart P+ type regions formed in the surface of the N type layer, each of the P+ type regions being continguous with and situated at opposite sides of, the P type region; a third N+ type region formed in the surface of the P type region; electrical contacts for the second, third, and each of the P+ type regions; and a protective oxide layer formed on the exposed regions of the surface of the N type layer.

Claim 9

A transistor arrangement capable of use in a saturated mode logic array in a programmable logic array having a relatively low charge storage period including an N.P.N. transistor having the base thereof connected to the emitter of a P.N.P. transistor and to an input terminal, the collector thereof connected to the base of the P.N.P. transistor and to an electrical supply terminal, and the emitter thereof connected to the collector of the P.N.P. transistor and to another electrical supply terminal, the transistor arrangement in the form of an integrated circuit which includes a semiconductor substrate of P type conductivity having an electrically conductive layer formed on one of the major surfaces thereof and a semiconductive layer of N type conductivity formed on the other major surface thereof; a first N+ type region situated at the interface of the substrate and the N type layer; a second N+ type region formed in the surface of the N type layer and extending to the first region; a P type region formed in the surface of the N type layer, the first region being partially overlapped by the P type region; two spaced-apart P+ type regions formed in the surface of the N type layer, each of the P+ type regions being continguous with and situated at opposite sides of, the P type region; a third N+ type region formed in the surface of the P type region; electrical contacts for the second, third, and each of the P+ type regions; and a protective oxide layer formed on the exposed regions of the surface of the N type layer.