Bidirectional vertical power MOS device and fabrication method

Claim 1

In a vertical MOSFET device including a silicon wafer having first and second opposing major surfaces, a source electrode disposed on the first surface, a drain electrode disposed on the second surface and an internally disposed insulated gate comprising a conductive electrode surrounded by a gate insulator, the silicon disposed between the insulated gate and each of the major surfaces being monocrystalline and of first conductivity type and the silicon disposed laterally adjacent to the insulated gate being monocrystalline and of second conductivity type, such that a predetermined voltage applied to the insulated gate creates an inversion channel for a predetermined distance in the laterally adjacent silicon, the improvement comprising: a relatively lightly doped region disposed in that portion of the laterally adjacent silicon where the inversion channel is formed and relatively heavy doping in other areas of the laterally adjacent silicon; a relatively lightly doped first voltage-supporting region disposed in that portion of the silicon that is contiguous with the insulated gate and is between both the insulated gate and the first wafer surface and the laterally adjacent silicon and the first wafer surface and a relatively heavily doped silicon region between the first voltage-supporting region and the first surface; a relatively lightly doped second voltage-supporting region disposed in that portion of the silicon that is contiguous with the insulated gate and is between both the insulated gate and the second wafer surface and the laterally adjacent silicon and the first wafer surface and a relatively heavily doped silicon region between the second voltage-supporting region and the second surface; and an interface between the gate insulator and the laterally adjacent silicon that has a low density of interface states.