US4634474A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Coating of III-V and II-VI compound semiconductors
Assignee: Nokia Bell Labs
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Filing: 1984-10-09
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Granted: 1987-01-06
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Expires: 2004-10-09
Abstract
Abstract Proposed is a method of fabricating III-V and II-VI compound semiconductors and a resulting product where there is formed on the surface a coating which can function as a diffusion mask and/or a passivation layer. The coating is a silicon layer deposited by a method which does not damage the semiconductor surface.
Inventors
- 👤 Irfan Camlibel
- 👤 Aland K. Chin
- 👤 Shobha Singh
- 👤 LeGrand G. Van Uitert
- 👤 George J. Zydzik
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:48
CPC Classifications
H; H10; H10W; H10W74/00; H10P; H10P14/00; H10P14/60; H10P14/69; H10P95/00; H10P95/90; H10P95/904; Y; Y10; Y10S; Y10S438/00; Y10S438/902; Y10S438/942; Y10S438/945
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
85 words
A method for fabricating III-V and II-VI compound semiconductor devices comprising the steps of forming a layer comprising silicon on a major surface of a semiconductor substrate comprising a material selected from the group consisting of III-V and II-VI compounds in a manner which does not cause significant damage to the semiconductor surface and subsequently heating the structure without causing significant diffusion of the silicon layer into the surface of the semiconductor and without converting any significant amount of the silicon layer to silicon oxide.
Claim 2
Independent Claim
85 words
A method for fabricating III-V and II-VI compound semiconductor devices comprising the steps of forming a layer comprising silicon on a major surface of a semiconductor substrate comprising a material selected from the group consisting of III-V and II-VI compounds in a manner which does not cause significant damage to the semiconductor surface and subsequently heating the structure without causing significant diffusion of the silicon layer into the surface of the semiconductor and without converting any significant amount of the silicon layer to silicon oxide.
Claim 3
Dependent Claim
33 words
The method according to claim 1 wherein an opening is formed in the silicon layer and impurities are introduced into the semiconductor through the opening while the silicon layer acts as a mask.
Claim 4
Dependent Claim
29 words
The method according to claim 2 wherein the structure is heated to a temperature within the range 200-1,000 degrees C. for a time within the range 1 min.-100 hrs.
Claim 5
Dependent Claim
18 words
The method according to claim 1 wherein the thickness of the layer is within the range 100-10,000 Angstroms.
Claim 6
Dependent Claim
14 words
The method according to claim 1 wherein the layer is deposited by electron-beam evaporation.
Claim 7
Dependent Claim
43 words
The method according to claim 1 wherein the structure is heated to a temperature within the range 200-1,000 degrees C. for a time of 1 min.-100 hrs. in order to anneal the semiconductor while the silicon layer prevents out-diffusion of the semiconductor components.
Claim 8
Dependent Claim
14 words
The method according to claim 1 wherein the layer consists essentially of undoped silicon.
Claim 9
Independent Claim
106 words
A method of fabricating III-V and II-VI compound semiconductor devices comprising the steps of: forming a layer consisting essentially of undoped silicon on a major surface of a semiconductor substrate comprising a material selected from the group consisting of III-V and II-VI compounds; forming an opening in said layer; diffusing an impurity into the portion of the semiconductor exposed by said opening by heating the structure to a temperature within the range 200-1,000 degrees C. for a time of 1 min.-100 hrs. while no significant amount of the silicon diffuses into the semiconductor and no significant amount of the silicon layer is converted to silicon dioxide.
Claim 10
Independent Claim
106 words
A method of fabricating III-V and II-VI compound semiconductor devices comprising the steps of: forming a layer consisting essentially of undoped silicon on a major surface of a semiconductor substrate comprising a material selected from the group consisting of III-V and II-VI compounds; forming an opening in said layer; diffusing an impurity into the portion of the semiconductor exposed by said opening by heating the structure to a temperature within the range 200-1,000 degrees C. for a time of 1 min.-100 hrs. while no significant amount of the silicon diffuses into the semiconductor and no significant amount of the silicon layer is converted to silicon dioxide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-05 | 1990-07-07 | 1991-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-05 | 1994-07-07 | 1995-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-05 | 1998-07-07 | 1999-01-06 | $7700.00 | Window Closed / Lapsed |