CMOS dynamic circulating-one shift register

Claim 2

A dynamic, circulating-one N-stage shift register (10) for circulating a plurality of N-1 logic zeroes and a single logic one through the N stages, said shift register comprising a plurality of N-1 shift register cells, (12 1 -12 N-1 ), each cell comprising a D input, a Q output, a Clear input, and a Set output, said plurality of N-1 shift register cells sequentially disposed such that the Q output of a first shift register cell (Q1) is connected to the D input of a second shift register cell (D2), and continuing in a like manner where the Q output of the N-2nd shift register cell (Q N-2 ) is connected to the D input of the N-1st shift register cell, for passing the value appearing at the associated D input to the associated Q output at the completion of both a master clock (MC) phase and a slave clock (SC) phase, where said master clock and said slave clock phases are non-overlapping; and a shift register control cell (14) comprising a D input, a Q output, and control means, wherein the Q output from the N-1st shift register cell (Q N-1 ) is connected to the D input of said control cell and the Q output from said control cell is connected to both the D input of the first shift register cell (D1) and the pluarlity of N-1 Clear inputs of said plurality of N-1 shift register cells for clearing the Q output of each shift register cell to the value of logic zero when the Q output of said shift register control cell (Q N ) is equal to a logic one, said shift register control cell control means responsive to the plurality of N-1 Set outputs from said plurality of N-1 shift register cells for providing a Q output from said control cell equal to a logic one when the plurality of N-1 Q outputs from said plurality of N-1 shift register cells are all equal to a logic zero.

Claim 3

A dynamic circulating-one N-stage shift register in accordance with claim 1 wherein each shift register cell (12 1 -12 N-1 , 14) of the plurality of N shift register cells comprises a master stage including a transmission gate (16) responsive to the associated D input and activated by the master clock, and an inverter buffer (22) connected to the output of said transmission gate; and a slave stage including a transmission gate (30) responsive to the output from said master stage inverter buffer and activated by the slave clock, and an inverter buffer (36) connected to the output of said slave stage transmission gate, wherein the output from said slave stage inverter buffer is defined as the associated Q output signal.

Claim 4

A dynamic circulating-one N-stage shift register as defined in claim 2 wherein each transmission gate comprises a P-channel MOS transistor (18,32) and an N-channel MOS transistor (20,34), where the drain of said P-channel transistor is connected to the source of said N-channel transistor and is responsive to the associated input signal, the source of said P-channel transistor is connected to the drain of said N-channel transistor and provides the associated output signal, the gate of said N-channel transistor being activated by the associated clock signal (MC,SC) and the gate of said P-channel transistor being activated by the complement of said associated clock signal (MC,SC); and each inverter buffer comprises a P-channel MOS transistor (24,38) and an N-channel MOS transistor (26,40) connected in series such that the drain of said P-channel transistor is connected to a positive power supply (VDD), the gate of said P-channel transistor is connected to both the gate of said N-channel transistor and the output of the associated transmission gate, the source of said N-channel transistor is connected to a negative power supply (VSS), and the drain of said N-channel transistor is connected to the source of said P-channel transistor where this interconnection provides the associated output.

Claim 5

A dynamic circulating-one N-stage shift register as defined in claim 2 wherein each of the plurality of N-1 shift register cells further comprises a first switching means connected between a positive power supply (VDD) and the input of the slave stage inverter buffer, said first switching means responsive at the Clear input applied to the shift register cell to the Q output from said control cell for connecting the input of said slave stage inverter buffer to said positive power supply when said Q output from said control cell is equal to a logic one, thus providing a Q output of said associated shift register cell equal to a logic zero; and a second switching means connected between a negative power supply (VSS) and the Set output of said associated shift register cell, said second switching means activated by the Q output of said associated shift register cell for providing a Set output of logic zero when said Q output of said associated shift register cell is equal to a logic one and a Set output equal to a logic one when said Q output of said associated shift register cell is equal to a logic zero.

Claim 6

A dynamic circulating-one N-stage shift register as defined in claim 4 wherein each first switching means comprises an N-channel MOS transistor (42) where the drain of said N-channel transistor is connected to the positive power supply, the source of said N-channel transistor is connected to the input of the associated slave stage inverter buffer, and the gate of said N-channel transistor is activated by the Q output from the control cell; and each second switching means comprises an N-channel MOS transistor (44) where the drain of said N-channel transistor is connected to the Set output of the associated shift register cell, the source of said N-channel transistor is connected to the negative power supply, and the gate of said N-channel transistor is activated by the Q output of said associated shift register cell.

Claim 7

A dynamic circulating-one N-stage shift register as defined in claim 2 wherein the shift register control cell further comprises control means (46-72) responsive to both the output of the control cell slave stage transmission gate and the plurality of N-1 Set outputs from the plurality of N-1 shift register cells for comparing said plurality of N-1 Set outputs to said output from said slave stage transmission gate for producing a Q output of said control cell equal to a logic one if and only if the plurality of N-1 Q outputs from said plurality of N-1 shift register cells are all equal to a logic zero value.

Claim 8

A dynamic circulating-one N-stage shift register as defined in claim 6 wherein the control means comprises a level-shifting inverter (46) responsive to the output of the slave stage transmission gate for providing a maximum negative output signal more positive than the negative power supply; threshold means (52) responsive both to the output from said level-shifting inverter and the plurality of N-1 Set outputs from the plurality of N-1 shift register cells for providing an output equal to a logic one if and only if the plurality of N-1 Q outputs from said plurality of N-1 shift register cells are all equal to a logic zero value; a first inverter buffer (54) responsive to the output from said threshold means for providing as an output the inverse of the output provided by said threshold means; a transmission gate (60) connected to the output of said first inverter buffer and activated by master clock for passing through as an output the inverted output from said threshold means during a master clock phase; a second inverter buffer (66) connected to the output of said transmission gate for providing as an output the threshold means output signal; and switching means connected between the negative power supply and the input of the slave stage inverter buffer, said switching means activated by the output of said second inverter buffer for connecting said input of said slave stage inverter buffer to said negative power supply if and only if the plurality of N-1 Q outputs from the plurality of N-1 shift register cells are all equal to a value of logic zero.

Claim 9

A dynamic circulating-one N-stage shift register as defined in claim 7 wherein the level-shifting inverter comprises a P-channel MOS transistor (48) and an N-channel MOS transistor (50) connected in series such that the drain of said P-channel transistor is connected to the positive power supply, the gate of said P-channel transistor is connected to both the gate of said N-channel transistor and the output of the slave stage transmission gate, the source of said N-channel transistor is connected to a power supply more positive than the negative power supply, and the source of said P-channel transistor is connected to the drain of said N-channel transistor where this interconnection provides a level-shifted output signal; the threshold means comprises an N-channel MOS transistor (52) which includes a channel length at least one order of magnitude greater than the channel length of any other transistor included in said shift register, the drain of said N-channel transistor connected to said positive power supply, the source of said N-channel transistor connected to the plurality of N-1 Set outputs from the plurality of N-1 shift register cells, and the gate of said N-channel transistor activated by the level-shifted output signal such that said threshold means provides an output value at said source equal to a logic one if and only if the plurality of N-1 Q outputs from the plurality of N-1 shift register cells are all equal to a logic zero; the first inverter buffer comprises a P-channel MOS transistor (56) and an N-channel MOS transistor (58) where the drain of said P-channel transistor is connected to said positive power supply, the gate of said P-channel transistor is connected to both the gate of said N-channel transistor and the output from said threshold means, the source of said N-channel transistor is connected to the negative power supply, and the drain of said N-channel transistor is connected to the source of said P-channel transistor for providing an output signal of logic one if and only if said plurality of N-1 Q outputs are all equal to a logic zero; the transmission gate comprises a P-channel MOS transistor (62) and an N-channel MOS transistor (64), the drain of said P-channel transistor connected to both the source of said N-channel transistor and the output from said first inverter buffer, the source of said P-channel transistor connected to the drain of said N-channel transistor, the gate of said N-channel transistor being activated by the master clock and the gate of said P-channel transistor being activated by the complement of said master clock for providing an output signal at the connection of P-channel source and N-channel drain during each positive phase of said master clock; the second inverter buffer comprises a P-channel MOS transistor (68) and an N-channel MOS transistor (70) where the drain of said P-channel transistor is connected to said positive power supply, the gate of said P-channel transistor is connected to both the gate of said N-channel transistor and the output from said transmission gate, the source of said N-channel transistor is connected to said negative power supply, and the drain of said N-channel transistor is connected to the source of said P-channel transistor for providing as an output an inverse value of the signal passing through said transmission gate during each positive of said master clock; and the switching means comprises an N-channel MOS transistor (72) where the source of said N-channel transistor is connected to said negative power supply, the drain of said N-channel transistor is connected to the input of said slave stage inverter buffer, and the gate of said N-channel transistor is activated by the output of said second inverter buffer, where said N-channel transistor is turned on if and only if said plurality of N-1 Q output signals are all equal to a logic zero, connecting said input of said slave stage inverter buffer to said negative power supply to provide a logic zero input to said slave stage inverter buffer and thus provide a Q output from the shift register control cell equal to a logic one.