Shift register with reduced number of components

Claim 2

A shift register comprising: a master section in which the drain electrode of a first P-channel MOS transistor having a source electrode connected to the high potential side of a power source is connected to the source electrode of a second P-channel MOS transistor at a first node, the drain electrode of said second P-channel MOS transistor is connected to the drain electrode of a first N-channel MOS transistor at a second node, the source electrode of said first N-channel MOS transistor is connected to the drain electrode of a second N-channel MOS transistor at a third node, and the source electrode of said second N-channel MOS transistor is connected to the low potential side of the power source; and a slave section in which the drain electrode of a third P-channel MOS transistor having a source electrode connected to the high potential side of the power source is connected to the source electrode of a fourth P-channel MOS transistor at a fourth node, the drain electrode of said fourth P-channel MOS transistor is connected to the drain electrode of a third N-channel MOS transistor at a fifth node, the source electrode of said third N-channel MOS transistor is connected to the drain electrode of a fourth N-channel MOS transistor at a sixth node, and the source electrode of said fourth N-channel MOS transistor is connected to the low potential side of the power source; wherein the respective gate electrodes of said first P-channel MOS transistor and said second N-channel MOS transistor are connected to each other at a seventh node, first and second clock pulses are applied to the respective gate electrodes of said second P-channel and first N-channel MOS transistors, the respective gate electrodes of said third P-channel MOS transistor and fourth N-channel MOS transistor are tied together and connected to said second node of the master section, and the second and first clock pulses are applied to respective gate electrodes of said fourth P-channel MOS transistor and third N-channel MOS transistor; whereby the master section and slave section form a 1-bit stage which is thereafter connected to a plurality of similarly constructed cascades; said first and third nodes of the master section, with the exception of the initial stage, being connected to a second node of the master section of the preceding stage through a fifth P-channel MOS transistor and fifth N-channel MOS transistor, respectively, with third and fourth clock pulses being applied to respective fifth P-channel MOS transistor and fifth N-channel MOS transistor thereby to produce an output at said fifth node.

Claim 3

A shift register according to claim 1, wherein the output of the final stage is connected to a first MOS inverter the output of which is connected to said second node through a first transmission gate composed of MOS transistors of opposite polarity.

Claim 4

A shift register comprising: a master section in which the drain electrode of a first P-channel MOS transistor having a source electrode connected to the high potential side of a power source is connected to the source electrode of a second P-channel MOS transistor at a first node, the drain electrode of said second P-channel MOS transistor is connected to the drain electrode of a first N-channel MOS transistor at a second node, the source electrode of said first N-channel MOS transistor is connected to the drain electrode of a second N-channel MOS transistor at a third node, and the source electrode of said second N-channel MOS transistor is connected to the low potential side of the power source; and a slave section in which the drain electrode of a third P-channel MOS transistor having a source electrode connected to the high potential side of the power source is connected to the source electrode of a fourth P-channel MOS transistor at a fourth node, the drain electrode of said fourth P-channel MOS transistor is connected to the drain electrode of a third N-channel MOS transistor at a fifth node, the source electrode of said third N-channel MOS transistor is connected to the drain electrode of a fourth N-channel MOS transistor at a sixth node, and the source electrode of said fourth N-channel MOS transistor is connected to the low potential side of the power source; wherein the respective gate electrodes of said first P-channel MOS transistor and said second N-channel MOS transistor are connected to each other at a seventh node, first and second clock pulses are applied to the respective gate electrodes of said second P-channel and first N-channel MOS transistors, the respective gate electrodes of said third P-channel MOS transistor and fourth N-channel MOS transistor are tied together and connected to said second node of the master section, and the second and first clock pulses are applied to respective gate electrodes of said fourth P-channel MOS transistor and third N-channel MOS transistor; whereby the master section and slave section form a 1-bit stage which is thereafter connected to a plurality of similarly constructed cascades; said fourth and sixth nodes of the slave section, with the exception of the initial stage, being connected respectively through fifth P-channel MOS transistor and fifth N-channel MOS transistor to said seventh node and hence to an output of the slave section of the preceding stage, with third and fourth clock pulses being applied to respective fifth P-channel and N-channel transistors thereby to produce an output at said fifth node.

Claim 5

A shift register comprising: a master section in which the drain electrode of a first P-channel MOS transistor having a source electrode connected to the high potential side of a power source is connected to the source electrode of a second P-channel MOS transistor at a first node, the drain electrode of said second P-channel MOS transistor is connected to the drain electrode of a first N-channel MOS transistor at a second node, the source electrode of said first N-channel MOS transistor is connected to the drain electrode of a second N-channel MOS transistor at a third node, and the source electrode of said second N-channel MOS transistor is connected to the low potential side of the power source; and a slave section in which the drain electrode of a third P-channel MOS transistor having a source electrode connected to the high potential side of the power source is connected to the source electrode of a fourth P-channel MOS transistor at a fourth node, the drain electrode of said fourth P-channel MOS transistor is connected to the drain electrode of a third N-channel MOS transistor at a fifth node, the source electrode of said third N-channel MOS transistor is connected to the drain electrode of a fourth N-channel MOS transistor at a sixth node, and the source electrode of said fourth N-channel MOS transistor is connected to the low potential side of the power source; wherein the respective gate electrodes of said first P-channel MOS transistor and said second N-channel MOS transistor are connected to each other at a seventh node, first and second clock pulses are applied to the respective gate electrodes of said second P-channel and first N-channel MOS transistors, the respective gate electrodes of said third P-channel MOS transistor and fourth N-channel MOS transistor are tied together and connected to said second node of the master section, and the second and first clock pulses are applied to respective gate electrodes of said fourth P-channel MOS transistor and third N-channel MOS transistor; whereby the master section and slave section form a 1-bit stage which is thereafter connected to a plurality of similarly constructed cascades; said fourth and sixth nodes of the slave section, with the exception of the initial stage, being connected respectively through fifth P-channel MOS transistor and fifth N-channel MOS transistor to said seventh node and hence to an output of the slave section of the preceding stage, with third and fourth clock pulses being applied to respective fifth P-channel and N-channel transistors thereby to produce an output at said fifth node.

Claim 6

A shift register according to claim 3, wherein the output of the final stage is series connected to first and second MOS inverters which produce an output signal connected back to the final stage output terminal through a first transmission gate composed of MOS transistors of opposite polarity.

Claim 7

A shift register comprising: a master section in which the drain electrode of a first P-channel MOS transistor having a source electrode connected to the high potential side of a power source is connected to the source electrode of a second P-channel MOS transistor at a first node, the drain electrode of said second P-channel MOS transistor is connected to the drain electrode of a first N-channel MOS transistor at a second node, the source electrode of said first N-channel MOS transistor is connected to the drain electrode of a second N-channel MOS transistor at a third node, and the source electrode of said second N-channel MOS transistor is connected to the low potential side of the power source; and a slave section in which the drain electrode of a third P-channel MOS transistor having a source electrode connected to the high potential side of the power source is connected to the source electrode of a fourth P-channel MOS transistor at a fourth node, the drain electrode of said fourth P-channel MOS transistor is connected to the drain electrode of a third N-channel MOS transistor at a fifth node, the source electrode of said third N-channel MOS transistor is connected to the drain electrode of a fourth N-channel MOS transistor at a sixth node, and the source electrode of said fourth N-channel MOS transistor is connected to the low potential side of the power source; wherein the respective gate electrodes of said first P-channel MOS transistor and said second N-channel MOS transistor are connected to each other at a seventh node, first and second clock pulses are applied to the respective gate electrodes of said second P-channel and first N-channel MOS transistors, the respective gate electrodes of said third P-channel MOS transistor and fourth N-channel MOS transistor are tied together and connected to said second node of the master section, and the second and first clock pulses are applied to respective gate electrodes of said fourth P-channel MOS transistor and third N-channel MOS transistor; whereby the master section and slave section form a 1-bit stage which is thereafter connected to a plurality of similarly constructed cascades; said fifth node of the final stage being connected to a first MOS inverter which is in turn connected to a second MOS inverter, the common connection of said inverters being connected to said second node through a first transmission gate composed of MOS transistors of opposite polarity, and the output of said second MOS inverter and input of said first MOS inverter being connected together through a second transmission gate composed of MOS transistors of opposite polarity.

Claim 8

A shift register comprising: a master section in which the drain electrode of a first P-channel MOS transistor having a source electrode connected to the high potential side of a power source is connected to the source electrode of a second P-channel MOS transistor at a first node, the drain electrode of said second P-channel MOS transistor is connected to the drain electrode of a first N-channel MOS transistor at a second node, the source electrode of said first N-channel MOS transistor is connected to the drain electrode of a second N-channel MOS transistor at a third node, and the source electrode of said second N-channel MOS transistor is connected to the low potential side of the power source; and a slave section in which the drain electrode of a third P-channel MOS transistor having a source electrode connected to the high potential side of the power source is connected to the source electrode of a fourth P-channel MOS transistor at a fourth node, the drain electrode of said fourth P-channel MOS transistor is connected to the drain electrode of a third N-channel MOS transistor at a fifth node, the source electrode of said third N-channel MOS transistor is connected to the drain electrode of a fourth N-channel MOS transistor at a sixth node, and the source electrode of said fourth N-channel MOS transistor is connected to the low potential side of the power source; wherein the respective gate electrodes of said first P-channel MOS transistor and said second N-channel MOS transistor are connected to each other at a seventh node, first and second clock pulses are applied to the respective gate electrodes of said second P-channel and first N-channel MOS transistors, the respective gate electrodes of said third P-channel MOS transistor and fourth N-channel MOS transistor are tied together and connected to said second node of the master section, and the second and first clock pulses are applied to respective gate electrodes of said fourth P-channel MOS transistor and third N-channel MOS transistor; whereby the master section and slave section form a 1-bit stage which is thereafter connected to a plurality of similarly constructed cascades; said fifth node of the final stage being connected to a first MOS inverter which is in turn connected to a second MOS inverter, the common connection of said inverters being connected to said second node through a first transmission gate composed of MOS transistors of opposite polarity, and the output of said second MOS inverter and input of said first MOS inverter being connected together through a second transmission gate composed of MOS transistors of opposite polarity.