US3578984A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Master/slave switching circuit employing insulated-gate field-effect transistors
Assignee: Plessey Overseas Ltd
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Filing: 1968-12-09
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Granted: 1971-05-18
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Expires: 1988-12-09
Abstract
Abstract A master/slave switching circuit comprising a master bistable defined by a pair of insulated gate field-effect transistors having associated with them load field-effect transistors and a slave bistable switch defined by a further pair of field-effect transistors also having insulated gate field-effect transistor loads connected there to the master bistable and the slave bistable being interconnected by insulated gate field-effect transistors such that if the state of the master bistable is changed in response to a clock pulse applied to a terminal the state of the slave bistable is also changed, the response of the master bistable to input clock pulses being controlled in accordance with the state of input signals applied to terminals.
Inventors
- 👤 John E Ryley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:37
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3562; G; G11; G11C; G11C19/00; G11C19/28; H03K3/356017; H03K3/356026
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
74 words
A master/slave switching circuit arrangement as claimed in claim 1 wherein clock pulses are applied to the master switch through interconnected gate contacts of a pair of gating IGFET''s having their drain contacts connected respectively to the source contacts of the IGFET''s of the master pair and their source contacts connected to a first supply rail of opposite polarity to a second supply rail to which the master and slave load means are connected.
Claim 2
Dependent Claim
56 words
A master/slave switching circuit arrangement as claimed in claim 2 wherein each gating IGFET has connected in parallel with it one or more further gating IGFET''s such that the presence or absence of a signal on the gate contacts of these further gating IGFET''s controls the response of the master switch to an applied clock pulse.
Claim 3
Dependent Claim
53 words
A master/slave switching circuit arrangement as claimed in claim 3 wherein the load means comprises two IGFET''s hereinafter called the master load IGFET''s, which are associated respectively with a different one of the IGFET''s of the master pair and wherein the further load means comprises two IGFET''s hereinafter called the slave load IGFET''s.
Claim 4
Dependent Claim
70 words
A master/slave switching circuit arrangement as claimed in claim 4 wherein each of the slave load IGFET''s and each of the master load IGFET''s has its respective gate contact and drain contact connected to the said second supply rail its source contact being directly connected to the drain contact of the particular IGFET of the master pair or slave pair as the case may be with which it is associated.
Claim 5
Dependent Claim
44 words
A master/slave switching circuit arrangement as claimed in claim 5 wherein the coupling means interconnecting the slave and master switches comprise two IGFET''s herein called coupling IGFET''s which are arranged to interconnect the IGFET''s of the master pair with IGFET''s of the slave pair.
Claim 6
Dependent Claim
118 words
A master/slave switching circuit arrangement as claimed in claim 6 wherein one of the coupling IGFET''s has its gate contact connected to the drain contact of one of the IGFET''s of the master pair the source contacts of one of the coupling IGFET''s and the said one IGFET of the master pair being interconnected and the drain contact of the said one coupling IGFET being connected to the drain contact of one IGFET of the slave pair, thereby to couple one IGFET of the master pair with one IGFET of the slave pair, the other IGFET of the master pair and the other IGFET of the slave pair being similarly coupled by means of the other coupling IGFET.
Claim 7
Dependent Claim
33 words
A master/slave circuit arrangement as claimed in claim 7 comprising two additional pairs of IGFET''s utilized for ''''preset'''' and ''''clear'''' purposes and hereinafter referred to as first and second pairs of reset IGFET''s.
Claim 8
Dependent Claim
113 words
A master/slave circuit arrangement as claimed in claim 8 wherein the first reset pair of IGFET''s have their respective drain contacts connected respectively to the drain contacts of the IGFET''s of the master pair, their source contacts being connected to the said first supply rail and the second reset pair being similarly connected to the slave pair of IGFET''s, the gate contact of one IGFET of the first reset pair and the gate contact of one IGFET of the second reset pair being interconnected to form a clear pulse input line and the other gate electrodes of the first and second reset pairs of IGFET''s being interconnected to define a preset input line.
Claim 9
Dependent Claim
37 words
A master/slave switching circuit arrangement as claimed in claim 7, wherein the drain contacts of said slave pair of IGFET''s are cross connected with the gate contacts of the further gating IGFET''s to define a J-K flip-flop.
Claim 10
Dependent Claim
56 words
A plurality of master/slave circuit arrangements as claimed in claim 1 wherein the said circuit arrangements are connected serially, with the output of one said circuit arrangement feeding the input of another said circuit arrangement, clock pulses being applied to the said circuit arrangements over a common clock pulse line thereby to define a shift register.
References Cited (Backward Citations)
US336315A
Cited
US3191061A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-17 | 1974-11-16 | 1975-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-17 | 1978-11-16 | 1979-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-17 | 1982-11-16 | 1983-05-18 | $7700.00 | Window Closed / Lapsed |