Dynamic shift register

Claim 2

A dynamic shift register, comprising: a. a first source of clock pulses, b. a second source arranged to supply clock pulses the phase of which is different from that of the clock pulses supplied by said first source, c. a plurality of cascaded stages, each stage being connected to both of said sources, each stage including an input terminal and an output terminal and also including: 1. first means for storing a charge in response to a pulse from said first source, 2. second means fOr storing a charge in response to a pulse from said second source, 3. third means for (a) conducting and storing part of the charge stored by said second means in response to a pulse from said first source, and (b) discharging the charge stored by said second and third means in response to a pulse from said first source and the energization of the input terminal of said stage, 4. fourth means for discharging the charge stored by said first means in response to a pulse from said second source and the presence of a charge stored by said third means, and 5. fifth means responsive to a pulse from said second source for providing a conductive path to said output terminal for the charge stored by said first means.

Claim 3

second means fOr storing a charge in response to a pulse from said second source,

Claim 4

second means fOr storing a charge in response to a pulse from said second source,

Claim 5

The register of claim 1 wherein said first and second means each comprise a capacitor and an insulated gate field effect transistor whose source-drain is connected between one of said sources and said capacitor.

Claim 6

third means for (a) conducting and storing part of the charge stored by said second means in response to a pulse from said first source, and (b) discharging the charge stored by said second and third means in response to a pulse from said first source and the energization of the input terminal of said stage,

Claim 7

third means for (a) conducting and storing part of the charge stored by said second means in response to a pulse from said first source, and (b) discharging the charge stored by said second and third means in response to a pulse from said first source and the energization of the input terminal of said stage,

Claim 8

The register of claim 1 wherein said third means comprises three insulated gate field effect transistors and a capacitor, the source-drain circuit of a first of said transistors being connected between said second means and one terminal of said capacitor, the source-drain circuits of the second and third of said transistors being connected in series between said second means and a terminal common to both of said sources, the gate electrode of the second of said transistors being connected to said second means.

Claim 9

The register of claim 1 wherein said fifth means comprises an insulated gate field effect transistor whose source-drain circuit is connected between said first means and said output terminal and whose gate electrode is connected to said second source.

Claim 10

fourth means for discharging the charge stored by said first means in response to a pulse from said second source and the presence of a charge stored by said third means, and

Claim 11

fourth means for discharging the charge stored by said first means in response to a pulse from said second source and the presence of a charge stored by said third means, and

Claim 12

fifth means responsive to a pulse from said second source for providing a conductive path to said output terminal for the charge stored by said first means.

Claim 13

fifth means responsive to a pulse from said second source for providing a conductive path to said output terminal for the charge stored by said first means.

Claim 14

The register of claim 1 wherein: a. said first means comprises a first capacitor and a first insulated gate field effect transistor whose source-drain circuit is connected between said second source and one terminal of said first capacitor, b. said second means comprises a second capacitor and a second insulated gate field effect transistor whose source-drain circuit is connected between said second source and one terminal of said second capacitor, c. said third means comprises third, fourth, and fifth insulated gate field effect transistors and a third capacitor, the source-drain circuit of said third transistor being connected between said one terminal of said second capacitor and one terminal of said third capacitor, the source-drain circuits of said fourth and fifth transistors being connected in series between said one terminal of said second capacitor and a point common to both of said sources, d. said fourth means comprises sixth and seventh insulated gate field transistors, the source-drain circuits of said sixth and seventh transistors being connected in series between said one terminal of said first capacitor and said point common to both of said sources, e. said fifth means comprises an eighth insulated gate field effect transistor whose source-drain circuit is connected between said one terminal of said first capacitor and said output terminal.

Claim 15

A dynamic shift register, comprising: a. a plurality of cascaded stages, each stage including first and second half stages, each stage having an input terminal, and output terminal, and a reference potential terminal, b. means for supplying information encoded in pulse form to the input terminal of a first of said stages and for supplying first and second mutually out-of-phase trains of clock pulses to each of said stages, c. each half stage including first, second, third, and fourth insulated gate field effect transistors, the source-drain circuits of said first, second, and third transistors of the first half of each stage being connected in series between said reference terminal and a supply point for said second clock pulse train, the source-drain circuits of said first, second, and third transistors of the second half of each stage being connected in Series between said reference terminal and a supply point for said first clock pulse train, the source-drain circuit of the fourth transistor of the first half of each stage being connected between the source electrode of the third transistor of said first half of each stage and the gate electrode of the first transistor of said second half of each stage, the source-drain circuit of the fourth transistor of the second half of each stage being connected between the source electrode of the third transistor of the second half of each stage and the output terminal of each stage, d. means for supplying said first clock pulse train to the gate electrodes of the second and fourth transistors of the first half of each stage and to the gate electrode of the third transistor of the second half of each stage, e. means for supplying said second clock pulse train to the gate electrodes of the second and fourth transistors of the second half of each stage and to the gate electrode of the third transistor of the first half of each stage, and f. means providing a capacitance between the gate electrode of the first transistor of each half of each stage and said common potential point, and g. means providing a capacitance between the source electrode of the third transistor of each half of each stage and another terminal of each stage.

Claim 16

A dynamic shift register, comprising: a. a plurality of cascaded stages, each stage including first and second half stages, each stage having an input terminal, and output terminal, and a reference potential terminal, b. means for supplying information encoded in pulse form to the input terminal of a first of said stages and for supplying first and second mutually out-of-phase trains of clock pulses to each of said stages, c. each half stage including first, second, third, and fourth insulated gate field effect transistors, the source-drain circuits of said first, second, and third transistors of the first half of each stage being connected in series between said reference terminal and a supply point for said second clock pulse train, the source-drain circuits of said first, second, and third transistors of the second half of each stage being connected in Series between said reference terminal and a supply point for said first clock pulse train, the source-drain circuit of the fourth transistor of the first half of each stage being connected between the source electrode of the third transistor of said first half of each stage and the gate electrode of the first transistor of said second half of each stage, the source-drain circuit of the fourth transistor of the second half of each stage being connected between the source electrode of the third transistor of the second half of each stage and the output terminal of each stage, d. means for supplying said first clock pulse train to the gate electrodes of the second and fourth transistors of the first half of each stage and to the gate electrode of the third transistor of the second half of each stage, e. means for supplying said second clock pulse train to the gate electrodes of the second and fourth transistors of the second half of each stage and to the gate electrode of the third transistor of the first half of each stage, and f. means providing a capacitance between the gate electrode of the first transistor of each half of each stage and said common potential point, and g. means providing a capacitance between the source electrode of the third transistor of each half of each stage and another terminal of each stage.

Claim 17

The register of claim 6 wherein said means of clause (f) is the gate electrode capacitance of the first transistor of each half of each stage.

Claim 18

The register of claim 6 wherein said other terminal of said means of clause (g) comprises an interconnection between said source electrode of the third transistor and an electrode of the fourth transistor of each half of each stage.

Claim 19

The register of claim 6 wherein said other terminal of clause (g) is a common connection point for the gate electrodes of the second and fourth transistors of the first half of each stage and the gate electrode of the third transistor of the second half of each stage, said means of clause (f) is the gate electrode capacitance of the first transistor of each half of each stage, and one electrode of said means of clause (g) comprises an interconnection between said source electrode of the third transistor and an electrode of the fourth transistor of each half of each stage.

Claim 20

The register of claim 6, each stage further including (1) a first additional insulated gate field effect transistor, the source-drain circuit of which is connected between the drain electrode of said first transistor of said first half of each stage and said gate electrode of said first transistor of said second half of each stage, the gate electrode of which is connected to said supply point for said first clock pulse train, and (2) a second additional insulated gate field effect transistor, the source-drain circuit of which is connected between the drain electrode of said first transistor of said second half of each stage and the gate electrode of the first transistor of said first half of each succeeding stage, the gate electrode of which is connected to said supply point for said second clock pulse train, whereby the operating speed of said register may be increased.