Fabrication process for bipolar devices

Claim 1

A method for the fabrication of bipolar devices with ultra-shallow device junctions, the method comprising the steps of: forming a semiconductor substrate; defining on the substrate the peripheries of a plurality of semiconductor regions; successively ion-implanting the plurality of regions at temperatures low enough to preclude annealing or activation; and subsequently annealing the ion-implanted regions in one short thermal annealing step that minimizes further diffusion of the implanted materials; wherein the device is not exposed to high temperatures during processing, and therefore is produced with a minimum of defects.

Claim 2

A method for the fabrication of bipolar devices with ultra-shallow device junctions, the method comprising the steps of: forming a semiconductor substrate; defining on the substrate the peripheries of a plurality of semiconductor regions; successively ion-implanting the plurality of regions at temperatures low enough to preclude annealing or activation; and subsequently annealing the ion-implanted regions in one short thermal annealing step that minimizes further diffusion of the implanted materials; wherein the device is not exposed to high temperatures during processing, and therefore is produced with a minimum of defects.

Claim 6

A method for the fabrication of bipolar devices with ultra-shallow device junctions, the method comprising the steps of: forming a semiconductor substrate; defining on the substrate the peripheries of a base region and an emitter region within the base region; ion-implanting the base region at temperatures low enough to preclude annealing or activation; ion-implanting the emitter region at temperatures low enough to preclude annealing or activation; and subsequently annealing the ion-implanted base and emitter regions in one short thermal annealing step that minimizes further diffusion of the implanted materials; wherein the device is not exposed to high temperatures during processing, and therefore is produced with a minimum of defects.

Claim 7

A method for the fabrication of bipolar devices with ultra-shallow device junctions, the method comprising the steps of: forming a semiconductor substrate; defining on the substrate the peripheries of a base region and an emitter region within the base region; ion-implanting the base region at temperatures low enough to preclude annealing or activation; ion-implanting the emitter region at temperatures low enough to preclude annealing or activation; and subsequently annealing the ion-implanted base and emitter regions in one short thermal annealing step that minimizes further diffusion of the implanted materials; wherein the device is not exposed to high temperatures during processing, and therefore is produced with a minimum of defects.

Claim 11

A method for the fabrication of semiconductor devices with ultra-shallow device junctions, the method comprising the steps of: forming a semiconductor substrate; defining on the substrate the peripheries of a plurality of semiconductor regions; successively ion-implanting the plurality of regions at temperatures low enough to preclude annealing or activation; and subsequently annealing the ion-implanted regions in one short thermal annealing step that minimizes further diffusion of the implanted materials; wherein the device is not exposed to high temperatures during processing, and therefore is produced with a minimum of defects.

Claim 12

A method for the fabrication of semiconductor devices with ultra-shallow device junctions, the method comprising the steps of: forming a semiconductor substrate; defining on the substrate the peripheries of a plurality of semiconductor regions; successively ion-implanting the plurality of regions at temperatures low enough to preclude annealing or activation; and subsequently annealing the ion-implanted regions in one short thermal annealing step that minimizes further diffusion of the implanted materials; wherein the device is not exposed to high temperatures during processing, and therefore is produced with a minimum of defects.

Claim 13

A method for the fabrication of bipolar silicon devices with ultra-shallow junctions, the method comprising the steps of: forming an n- collector layer on an n+ silicon substrate; forming a mask oxide layer on the collector layer; selectively removing portions of the mask oxide layer to define at least one base moat area and at least one ballast resistor area; ion-implanting p- regions in the defined moat and ballast resistor areas; forming an oxide layer at low temperature over the entire structure; selectively removing portions of the oxide layer formed in the previous step, to define a base area within the moat region; subjecting the structure to prolonged heat to drive the implanted p- regions to a desired depth; forming an implant oxide layer over the base area and the ballast resistor area; ion-implanting a p+ base region and a p+ ballast resistor region through the implant oxide layer; forming another oxide layer at low temperature over the entire structure; selectively removing portions of the last-formed oxide layer, to define at least one emitter area within the base area; forming another oxide layer over the structure at low temperature; selectively removing portions of the last-formed oxide layer by reactive ion etching, to define an opening over the emitter periphery; ion-implanting an n type material to form an emitter region; forming a polycrystalline silicon layer over the structure; thermal pulse-annealing the ion-implanted regions to minmize further movement of junctions between regions; and defining contact areas over the base and emitter regions, for the subsequent formation of metal contact layers.

Claim 14

A method for the fabrication of bipolar silicon devices with ultra-shallow junctions, the method comprising the steps of: forming an n- collector layer on an n+ silicon substrate; forming a mask oxide layer on the collector layer; selectively removing portions of the mask oxide layer to define at least one base moat area and at least one ballast resistor area; ion-implanting p- regions in the defined moat and ballast resistor areas; forming an oxide layer at low temperature over the entire structure; selectively removing portions of the oxide layer formed in the previous step, to define a base area within the moat region; subjecting the structure to prolonged heat to drive the implanted p- regions to a desired depth; forming an implant oxide layer over the base area and the ballast resistor area; ion-implanting a p+ base region and a p+ ballast resistor region through the implant oxide layer; forming another oxide layer at low temperature over the entire structure; selectively removing portions of the last-formed oxide layer, to define at least one emitter area within the base area; forming another oxide layer over the structure at low temperature; selectively removing portions of the last-formed oxide layer by reactive ion etching, to define an opening over the emitter periphery; ion-implanting an n type material to form an emitter region; forming a polycrystalline silicon layer over the structure; thermal pulse-annealing the ion-implanted regions to minmize further movement of junctions between regions; and defining contact areas over the base and emitter regions, for the subsequent formation of metal contact layers.