US4497665A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing semiconductor device
Assignee: University College London
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Filing: 1983-01-03
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Granted: 1985-02-05
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Expires: 2003-01-03
Abstract
Abstract In a method of fabricating a semiconductor device having a V-groove insulating isolation structure with polycrystalline silicon filled in the groove of which the internal surface is covered with an insulating film of silicon dioxide, the method according to this invention comprises the steps of selectively ion implanting an impurity material into a desired region of the polycrystalline silicon layer in order to give to this region a desired different type of electric conductivity relative to the polycrystalline silicon layer followed by a selective annealing by an energy beam such as a laser of a desired part of the polycrystalline silicon layer including the region into which the impurity material has been ion implanted.
Inventors
- 👤 Takeshi Fukuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:57
CPC Classifications
H; H10; H10P; H10P34/00; H10P34/40; H10P34/42; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/065; H10W20/40; H10W20/49
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
125 words
A method of manufacturing interconnections for a plurality of semiconductor devices on a substrate, comprising the steps of: preparing said semiconductor substrate to have a first conductivity type and a semiconductor layer of a second conductivity type opposite to the first conductivity type, the layer being formed on the substrate, forming V-grooves penetrating through the semiconductor layer and reaching into the substrate for selectively separating said devices, forming an insulating film on the surface of the V-groove, forming a polycrystalline semiconductor layer on the insulating film in the V-grooves so as to substantially fill said V-grooves, and irradiating an energy beam onto selected surface portions of the polycrystalline semiconductor layer along said V-grooves to convert said selected portion to single-crystal semiconductor for forming said interconnections.
Claim 2
Independent Claim
125 words
A method of manufacturing interconnections for a plurality of semiconductor devices on a substrate, comprising the steps of: preparing said semiconductor substrate to have a first conductivity type and a semiconductor layer of a second conductivity type opposite to the first conductivity type, the layer being formed on the substrate, forming V-grooves penetrating through the semiconductor layer and reaching into the substrate for selectively separating said devices, forming an insulating film on the surface of the V-groove, forming a polycrystalline semiconductor layer on the insulating film in the V-grooves so as to substantially fill said V-grooves, and irradiating an energy beam onto selected surface portions of the polycrystalline semiconductor layer along said V-grooves to convert said selected portion to single-crystal semiconductor for forming said interconnections.
Claim 3
Dependent Claim
14 words
The method of the claim 1, wherein said energy beam is a laser beam.
Claim 4
Dependent Claim
31 words
The method of claim 1 further comprising the step of implanting impurity ions into the polycrystalline semiconductor layer at said selected surface portions before the step of irradiating the energy beam.
Claim 5
Dependent Claim
43 words
The method of claim 1, 2 or 3, comprising forming said single-crystal semiconductor to comprise a region of a first conductivity type in contact with said polycrystalline layer, and a further region of second conductivity type within said region of first conductivity type.
Claim 6
Dependent Claim
28 words
The method of claim 1, comprising forming insulating regions at the surface of said polycrystal semiconductor layer on both sides of said single-crystal semiconductor for insulating said devices.
Claim 7
Dependent Claim
28 words
The method of claim 4, comprising forming insulating regions at the surface of said polycrystal semiconductor layer on both sides of said single-crystal semiconductor for insulating said devices.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-05 | 1988-08-06 | 1989-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-05 | 1992-08-06 | 1993-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-05 | 1996-08-06 | 1997-02-05 | $7700.00 | Window Closed / Lapsed |