US4037306A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit and method
Assignee: Motorola Solutions Inc
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Filing: 1975-10-02
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Granted: 1977-07-26
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Expires: 1995-10-02
Abstract
Abstract An integrated circuit structure is provided in which component isolation is achieved after all diffused junction formation is complete. An anisotropically etched moat provides isolation. The surfaces of the moat are lined with oxide and a planar wafer surface is restored by filling the moat with metal. The subsurface metal region can then be used as a conductor for component interconnection.
Inventors
- 👤 Ronald J. Gutteridge
- 👤 George A. Stickney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:50
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W10/00; H10W10/01; H10W10/011; H10W10/10; H10W20/01; H10W20/021; H10W20/031; H10W20/056
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
205 words
A method for manufacturing an integrated circuit comprising the steps of: a. providing a semiconductor substrate having an upper layer; b. forming device junctions in said upper layer; c. forming an oxide layer over the surface of said upper layer; d. forming a metal masking layer over the surface of said oxide layer; e. forming a predetermined pattern of openings through said metal masking and oxide layers; f. forming recessed regions in the surface of said semiconductor substrate using said predetermined pattern of openings as a mask, said recessed regions extending below the surface through said upper layer thereby isolating device regions containing said device junctions; g. removing portions of said oxide layer overhanging the periphery of said recessed regions using said metal masking layer as a mask; h. removing said metal masking layer without removing said oxide layer; i. forming a thin insulating layer in said recessed regions; j. forming metal regions in said recessed regions, the surface of said metal regions coinciding with said surface of said upper layer; and k. electrically connecting said metal regions to a potential source to form an equipotential interconnecting network, said network selectively connectable to said device junctions and to other electrical components of said integrated circuit.
Claim 2
Independent Claim
205 words
A method for manufacturing an integrated circuit comprising the steps of: a. providing a semiconductor substrate having an upper layer; b. forming device junctions in said upper layer; c. forming an oxide layer over the surface of said upper layer; d. forming a metal masking layer over the surface of said oxide layer; e. forming a predetermined pattern of openings through said metal masking and oxide layers; f. forming recessed regions in the surface of said semiconductor substrate using said predetermined pattern of openings as a mask, said recessed regions extending below the surface through said upper layer thereby isolating device regions containing said device junctions; g. removing portions of said oxide layer overhanging the periphery of said recessed regions using said metal masking layer as a mask; h. removing said metal masking layer without removing said oxide layer; i. forming a thin insulating layer in said recessed regions; j. forming metal regions in said recessed regions, the surface of said metal regions coinciding with said surface of said upper layer; and k. electrically connecting said metal regions to a potential source to form an equipotential interconnecting network, said network selectively connectable to said device junctions and to other electrical components of said integrated circuit.
Claim 3
Dependent Claim
21 words
A method as recited in claim 1 wherein said metal masking layer is formed of an alloy of nickel and chromium.
Claim 4
Dependent Claim
31 words
A method as recited in claim 1 wherein said metal regions are formed of a metal whose melting point temperature is less than the temperature required to form a diffused junction.
Claim 5
Dependent Claim
13 words
A method as recited in claim 3 wherein said metal regions are aluminum.
Claim 6
Dependent Claim
24 words
A method as recited in claim 4 wherein said semiconductor substrate has a [100] surface and said recessed regions are formed by anisotrophic etching.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-25 | 1981-01-24 | 1981-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-25 | 1985-01-24 | 1985-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-25 | 1989-01-24 | 1989-07-26 | $7700.00 | Window Closed / Lapsed |