← Back to Patent Explorer
US3883948A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor structure and method

Assignee: Signetics Corp
•
Filing: 1974-01-02
•
Granted: 1975-05-20
•
Expires: 1994-01-02
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Semiconductor structure formed from a semiconductor body having an impurity of one conductivity type therein and having a major surface lying in a <100> plane. Moats are provided which extend through the major surface and have spaced side walls lying in a plane different from the <100 > plane and at said surface define spaced islands. Layers of protective material are formed on the side walls of the moats. Regions of said impurity of one conductivity type and of greater concentration than that in the body extend downwardly into the body from the protective layers. An insulating material fills the moats and devices are formed in the islands. An insulating layer is formed on said surface and lead means is provided on the insulating layer and extends through the insulating layer to make contact to the devices and extends over the material in said moats to interconnect the devices in the spaced islands. It is desirable that the moats have a generally rectangular configuration with inner and outer perimeters and inner and outer corners. The outer corners are defined by diagonal, generally planar wall portions which lie in either the <110> plane or the < 111> plane. If desired, the bottom of the moats can extend downwardly until the side walls form a Vee in cross-section.

Inventors

  • 👤 David F Allison

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 03:07
CPC Classifications
H; H10; H10D; H10D99/00; H10P; H10P95/00; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40; Y; Y10; Y10S; Y10S148/00; Y10S148/051; Y10S148/085; Y10S438/00; Y10S438/973

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 301 words
In a method for forming a semiconductor structure, providing a semiconductor body having an impurity of one conductivity type therein and having a major surface lying in a <100> plane, providing an etch resistant mask on said surface and having a predetermined pattern of openings for moats formed therein, bringing an anisotropic etch into contact with the portions of said surfaces lying in the <100> plane exposed by the mask to form moats in the semiconductor body having side walls lying in a plane different from the <100> plane and at said surface defining spaced islands, said side walls defining the moats extending downwardly into the semiconductor body until they join each other to form moats which are substantially V-shaped in cross section, forming protective layers upon said side walls defining the moats, etching away portions of the protective layers in the moats so that the portions of the protective layers at the apex of the moats are removed and the thickness of the protective layers on the side walls is reduced, causing an impurity of said one conductivity type to enter the semiconductor body through the apexes of the moats to form regions of said one impurity of one conductivity type of greater concentration than that of the semiconductor body extending downwardly from the layers of the moats, forming protective layers in the apexes of the moats and adjoining the protective layers on the side walls of the moats, filling the moats with a filling material, forming devices in said islands, providing protective layers overlying said islands and adjoining the protective layers in the moats and forming leads on said layers of protective material extending through said layers of protective material to make contact with said devices in said islands and interconnecting the devices with the devices in other islands.
Claim 2
Dependent Claim 301 words
In a method for forming a semiconductor structure, providing a semiconductor body having an impurity of one conductivity type therein and having a major surface lying in a <100> plane, providing an etch resistant mask on said surface and having a predetermined pattern of openings for moats formed therein, bringing an anisotropic etch into contact with the portions of said surfaces lying in the <100> plane exposed by the mask to form moats in the semiconductor body having side walls lying in a plane different from the <100> plane and at said surface defining spaced islands, said side walls defining the moats extending downwardly into the semiconductor body until they join each other to form moats which are substantially V-shaped in cross section, forming protective layers upon said side walls defining the moats, etching away portions of the protective layers in the moats so that the portions of the protective layers at the apex of the moats are removed and the thickness of the protective layers on the side walls is reduced, causing an impurity of said one conductivity type to enter the semiconductor body through the apexes of the moats to form regions of said one impurity of one conductivity type of greater concentration than that of the semiconductor body extending downwardly from the layers of the moats, forming protective layers in the apexes of the moats and adjoining the protective layers on the side walls of the moats, filling the moats with a filling material, forming devices in said islands, providing protective layers overlying said islands and adjoining the protective layers in the moats and forming leads on said layers of protective material extending through said layers of protective material to make contact with said devices in said islands and interconnecting the devices with the devices in other islands.
Claim 3
Dependent Claim 53 words
A method as in claim 1 wherein said openings in said mask are formed and positioned so that the moats are formed with a generally rectangular configuration and with inner and outer side walls with inner and outer corners and with a diagonal generally planar wall formed in each of the outer corners.
Claim 4
Dependent Claim 16 words
A method as in claim 2 wherein said diagonal wall portions lie in the <110> plane.
Claim 5
Dependent Claim 16 words
A method as in claim 2 wherein said diagonal wall portions lie in the <111> plane.
Claim 6
Dependent Claim 12 words
A method as in claim 3 wherein the inside corners are rounded.
Claim 7
Dependent Claim 19 words
A method as in claim 4 wherein the inside corners are in the form of right angles in plan.
Claim 8
Dependent Claim 275 words
In a method for the forming a semiconductor structure, providing a semiconductor body having an impurity of one conductivity type therein and having a major surface lying in the <100> plane, providing an etch resistant mask on said surface and having a predetermined pattern of openings for moats formed therein, utilizing an anisotropic etch to contact the portions of said surface exposed in said openings to form moats in a semiconductor body having a generally rectangular configuration with inner and outer inclined side walls lying in a plane different from the <100> plane and having outside corners with diagonal planar side wall portions formed in the outside corners and forming a layer of insulating material on the side walls and the diagonal planar side wall portions defining the moats, utilizing an etchant to contact the layer of insulating material in the moats to selectively remove the insulating material from the bottoms of the moats while retaining portions of the layer of insulating material on the side walls of the moats, causing an impurity of said one conductivity type to enter the Semiconductor body from the bottom of the moats to form regions of said impurity of one conductivity type of greater concentration than that in the body and extending downwardly from the insulating layers on the side walls of the moats, forming insulating material on the bottoms of the moats adjoining the insulating material on the side walls, filling the moats with an insulating material, forming devices in said islands, providing an insulating layer overlying said islands and adjoining the insulating material in the moats and providing means for interconnecting said devices in said islands.
Claim 9
Dependent Claim 275 words
In a method for the forming a semiconductor structure, providing a semiconductor body having an impurity of one conductivity type therein and having a major surface lying in the <100> plane, providing an etch resistant mask on said surface and having a predetermined pattern of openings for moats formed therein, utilizing an anisotropic etch to contact the portions of said surface exposed in said openings to form moats in a semiconductor body having a generally rectangular configuration with inner and outer inclined side walls lying in a plane different from the <100> plane and having outside corners with diagonal planar side wall portions formed in the outside corners and forming a layer of insulating material on the side walls and the diagonal planar side wall portions defining the moats, utilizing an etchant to contact the layer of insulating material in the moats to selectively remove the insulating material from the bottoms of the moats while retaining portions of the layer of insulating material on the side walls of the moats, causing an impurity of said one conductivity type to enter the Semiconductor body from the bottom of the moats to form regions of said impurity of one conductivity type of greater concentration than that in the body and extending downwardly from the insulating layers on the side walls of the moats, forming insulating material on the bottoms of the moats adjoining the insulating material on the side walls, filling the moats with an insulating material, forming devices in said islands, providing an insulating layer overlying said islands and adjoining the insulating material in the moats and providing means for interconnecting said devices in said islands.

References Cited (Backward Citations)

US3689992A Cited
US3386865A Cited
US3355636A Cited
US3416224A Cited
US3780426A Cited
US3659160A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-05-19 1978-11-18 1979-05-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-05-19 1982-11-18 1983-05-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-05-19 1986-11-18 1987-05-20 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag