US4606114A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multilevel oxide as diffusion source
Assignee: Texas Instruments Inc
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Filing: 1984-08-29
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Granted: 1986-08-19
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Expires: 2004-08-29
Abstract
Abstract A method of manufacture of a semiconductor device such as an MOS dynamic read/write memory cell array uses a doped multilevel oxide layer as a diffusion source to create source/drain regions and diffused interconnects. The process is thereby simplified since an ion implant ordinarily used for this purpose is avoided. The doped oxide subjected to a heat treatment for drive-in and densification, then is reflowed after contact holes are etched.
Inventors
- 👤 Karl H. Kraus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 00:50
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
106 words
A method of making a semiconductor device comprising the steps of: applying a conductor layer to a face of a semiconductor body and patterning said layer to define a mask for self-alignment, applying a coating of doped insulator to said face, heating said body to simultaneously cause densification of said device and diffusing of conductivity determining impurity from said insulator into said face, using said conductor layer as a mask, opening contact holes in said insulator, again heating said body for reflowing said doped insulator to smooth the contour of said sontact holes, and depositing a metallic layer over said insulator and into said contact holes.
Claim 2
Independent Claim
106 words
A method of making a semiconductor device comprising the steps of: applying a conductor layer to a face of a semiconductor body and patterning said layer to define a mask for self-alignment, applying a coating of doped insulator to said face, heating said body to simultaneously cause densification of said device and diffusing of conductivity determining impurity from said insulator into said face, using said conductor layer as a mask, opening contact holes in said insulator, again heating said body for reflowing said doped insulator to smooth the contour of said sontact holes, and depositing a metallic layer over said insulator and into said contact holes.
Claim 3
Dependent Claim
26 words
A method according to claim 1 wherein said heating step simultaneously drives said impurity into said conductor layer to establish a desired level of conductivity therein.
Claim 4
Dependent Claim
13 words
A method according to claim 1 wherein the insulator is phosphorus-doped silicon oxide.
Claim 5
Dependent Claim
12 words
A method according to claim 3 wherein the conductor is polycrystalline silicon.
Claim 6
Dependent Claim
12 words
A method according to claim 4 wherein the semiconductor body is silicon.
Claim 7
Dependent Claim
18 words
A method according to claim 5 wherein the conductor layer is the gate of an N-channel MOS transistor.
Claim 8
Dependent Claim
12 words
A method according to claim 6 wherein the metallic layer is aluminum.
Claim 9
Independent Claim
91 words
A method of making a MOS transistor device comprising the steps of: applying a coating of phosphorus-doped silicon oxide to a face of a semiconductor body, heating said body of simultaneously cause densification of said device and diffusing of conductivity determining impurity from said insulator into said face, using said conductor layer as a mask, opening contact holes in said insulator, again heating said body for reflowing said doped insulator to smooth the contour of said contact holes, and depositing a metallic layer over said insulator and into said contact holes.
Claim 10
Independent Claim
91 words
A method of making a MOS transistor device comprising the steps of: applying a coating of phosphorus-doped silicon oxide to a face of a semiconductor body, heating said body of simultaneously cause densification of said device and diffusing of conductivity determining impurity from said insulator into said face, using said conductor layer as a mask, opening contact holes in said insulator, again heating said body for reflowing said doped insulator to smooth the contour of said contact holes, and depositing a metallic layer over said insulator and into said contact holes.
Claim 11
Dependent Claim
18 words
A method according to claim 8 wherein the phosphorus-doped silicon oxide contains about 8% by weight of phosphorus.
Claim 12
Dependent Claim
12 words
A method according to claim 9 wherein the gate is polycrystalline silicon.
References Cited (Backward Citations)
US3887733A
Cited
US4055444A
Cited
US4361949A
Cited
US4224089A
Cited
US4204894A
Cited
US4273805A
Cited
US4271582A
Cited
US4348802A
Cited
US4355454A
Cited
US4388121A
Cited
US4404733A
Cited
US4455325A
Cited
US4499653A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-18 | 1990-02-17 | 1990-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-18 | 1994-02-17 | 1994-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-18 | 1998-02-17 | 1998-08-19 | $7700.00 | Window Closed / Lapsed |