Small dimension field effect transistor using phosphorous doped silicon glass reflow process

Claim 1

A process for fabricating semiconductor devices including a field effect transistor and first and second levels of interconnections on a semiconductor substrate comprising the steps of: forming a first layer of silicon oxide over said semiconductor substrate, forming a window in said first layer of silicon oxide, forming a second layer of silicon oxide on said semiconductor substrate in said window, forming a layer of polycrystalline silicon over said first and second layers of silicon oxide, defining said layer of polycrystalline silicon to form the gate electrode of said field effect transistor in said window and to form conductive paths to provide said first level of interconnections, forming a layer of silicon nitride over said first and second layers of silicon oxide, said gate electrode, and said first level of interconnections, forming a third layer of silicon oxide doped with phosphorus over said layer of silicon nitride, defining said third layer of silicon oxide including removing said third layer of silicon oxide over said window and outside said window by a predetermined distance, reflowing said third layer of silicon oxide whereby the upper surface of said third layer of silicon oxide is smoothed and its edges rounded, removing selected portions of said silicon nitride layer and of said second layer of silicon oxide to expose first and second areas of said semiconductor substrate in said window on each side of said gate electrode, forming first and second impurity regions below said first and second areas, respectively, to form the source and drain of said field effect transistor, forming a layer of metal over said third layer of silicon oxide, and said first and second impurity regions, and defining said layer of metal to form conductive paths to said first and second impurity regions and to form conductive paths to provide said second level of interconnections.