Dram with polysi bit lines and added junction capacitance

Claim 1

In a semiconductor memory device having at least two layers of polycrystalline silicon and having an insulated gate field effect transistor as a fundamental element formed on a substrate, an improvement comprising: a first layer of polycrystalline silicon serving as an electrode of a capacitor including an electric charge storage region, and a bit line, said first polycrystalline silicon layer extending over only a portion of said electric charge storage region, said electric charge storage region including a region not covered by said first polycrystalline layer, said not covered region formed in said substrate and having a conductivity type opposite that of said substrate and acting as an additive junction capacitor to increase the charge storage capacity of said charge storage region; and a second layer of polycrystalline silicon serving as a gate electrode of said transistor, said second layer of polycrystalline silicon partially covering said first layer of polycrystalline silicon and also not covering said additive junction capacitor; and said first and second polycrystalline silicon layers extending over and covering regions of said substrate which are all only of the substrate conductivity type.