Integrated circuit electrical capacitor, particularly as a storage element for semiconductor memories

Claim 1

A storage arrangement comprising: a semiconductor substrate of one conductivity type; a first insulating layer carried on said substrate; a plurality of capacitors arranged in a matrix of columns and rows, each of said capacitors including a first electrode carried on said first insulating layer, an inversion layer in said semiconductor substrate beneath said first insulating layer, a common terminal for all of said capacitors connected to said substrate, a first doped region in said substrate with doping of said opposite type of conductivity and extending up to and beneath said first Insulating layer and said first electrode, a second doped region with doping of said opposite conductivity type in said substrate extending up to and beneath and about said first electrode; a plurality of transistors arranged in a matrix of columns and rows, each of said transistors arranged adjacent a respective capacitor and including said substrate, the respective first doped region, a third doped region in said substrate spaced from the respective second doped region and of said opposite type of conductivity, a second electrode carried on said first insulating layer between said first and third doped regions, and a third electrode carried on said third doped region; a plurality of parallel spaced digit conductors carried within said substrate, each of said digit lines connecting aligned ones of said third doped regions; a second insulating layer covering said first electrodes; and a plurality of parallel spaced selection conductors connecting aligned ones of said second electrodes.