Semiconductor memory with selectively enabled precharge and sense amplifier circuits

Claim 2

A semiconductor integrated memory device comprising: a plurality of bit lines; a plurality of memory cells each connected to at least one of said bit lines; means for addressing said memory cells including a plurality of word lines divided into at least first and second sets, each of said memory cells being connected to at least one of said word lines, a plurality of means each for selectively enabling any of said work lines of said at least first and second sets, respectively; at least two precharge means, at least first and second groups of said bit lines connected to those of said memory cells associated with said at least first and second sets of said word lines being connected to said at least two precharge means, respectively, said precharge means for precharging the associated group of said bit lines to an initial level; and select means for selecting one of said bit line precharge means and a corresponding one of said enabling means.

Claim 3

The semiconductor integrated memory device according to claim 1 further including a plurality of input-output buses, each connected to a single one of said bit line groups, respectively, and a second select means for selecting one of said input-output buses.

Claim 4

The semiconductor integrated memory device according to claim 2 further comprising: a plurality of means each for individually precharging a single one of said input-output buses; and third select means for controlling which of said input-output bus precharging means is operative.

Claim 5

The semiconductor integrated memory device according to claim 3 further comprising an input-output circuit connected to said input-output buses through said second select means.

Claim 6

The semiconductor integrated memory device according to claim 1, 2, 3 or 4 further comprising: a plurality of sense amplifying means each for amplifying signals on a single one of said groups of bit lines, respectively; and fourth select means for selectively enabling one of said sense amplifying means.

Claim 7

The semiconductor integrated memory device according to claim 3 or 4 wherein said first, second and third select means are controlled by a select control signal.

Claim 8

The semiconductor integrated memory device according to claim 6 wherein said select control signal corresponds to signals for addressing said device.

Claim 9

The semiconductor integrated memory device according to claim 7 wherein said address signals are column address signals.

Claim 10

The semiconductor integrated memory device according to claim 7 wherein the address signals are row address signals.

Claim 11

A semiconductor integrated memory device comprising: a plurality of bit lines and row lines; row decoder means for selectively energizing said row lines; a plurality of memory cells, each connected to at least one of said bit lines and controlled by one of said row lines; at least two precharge means, each connected to a group of said bit lines for precharging said bit lines in said groups to an initial level, each of said precharge means being controlled by precharge control lines; first select means for selecting one of said precharge control lines; a plurality of input-output lines each connected to a single one of said bit line groups; a plurality of input-output line precharging means each associated with a single one of said input-output lines for precharging said input-output lines; second select means for selecting one of said input-output lines; third select means for selecting one of said input-output line precharge means; and a select control signal line connected to said first, second and third select means.

Claim 12

A semiconductor integrated memory device comprising: a plurality of bit lines and row lines; row decoder means for selectively energizing said row lines; a plurality of memory cells, each connected to at least one of said bit lines and controlled by one of said row lines; at least two precharge means, each connected to a group of said bit lines for precharging said bit lines in said groups to an initial level, each of said precharge means being controlled by precharge control lines; first select means for selecting one of said precharge control lines; a plurality of input-output lines each connected to a single one of said bit line groups; a plurality of input-output line precharging means each associated with a single one of said input-output lines for precharging said input-output lines; second select means for selecting one of said input-output lines; third select means for selecting one of said input-output line precharge means; and a select control signal line connected to said first, second and third select means.

Claim 13

The semiconductor integrated memory device according to claim 10 further comprising: sense amplifier circuits, at least one operative with each of said bit line groups; an enable control line associated with each of said sense amplifier circuits; and fourth select means for selection of said sense amplifier circuit enable control lines.

Claim 14

A semiconductor integrated memory device comprising: a plurality of bit lines; a plurality of row lines divided into at least first and second sets; a plurality of means each for selectively enabling any of said row lines of said at least first and second sets, respectively; a plurality of memory cells, each connected to at least one of said bit lines and controlled by one of said row lines; at least two precharge means, each connected to a group of said bit lines respectively connected to those of said memory cells associated with one of said at least first and second sets of row lines for precharging said bit lines in said groups to an initial level; first select means for selecting one of said precharge means and a corresponding one of said enabling means; input-output lines connected to said bit line groups; column decoder means for selecting one of said bit lines; one column buffer circuit connected between said decoder and said bit lines in each of said groups; and second select means for selecting one of said buffer circuits.

Claim 15

A semiconductor integrated memory device comprising: a plurality of bit lines; a plurality of row lines divided into at least first and second sets; a plurality of means each for selectively enabling any of said row lines of said at least first and second sets, respectively; a plurality of memory cells, each connected to at least one of said bit lines and controlled by one of said row lines; at least two precharge means, each connected to a group of said bit lines respectively connected to those of said memory cells associated with one of said at least first and second sets of row lines for precharging said bit lines in said groups to an initial level; first select means for selecting one of said precharge means and a corresponding one of said enabling means; input-output lines connected to said bit line groups; column decoder means for selecting one of said bit lines; one column buffer circuit connected between said decoder and said bit lines in each of said groups; and second select means for selecting one of said buffer circuits.

Claim 16

The semiconductor integrated memory circuit according to claim 12 further comprising a select control signal line connected to said first and second select means.

Claim 17

A semiconductor integrated memory device comprising: a plurality of bit lines; a plurality of memory cells each connected to at least one of said bit lines; means for addressing said memory cells; at least two precharge means, a predetermined group of said bit lines being connected to each of said precharge means, respectively, said precharge means for precharging the associated group of said bit lines to an initial level; first select means for selecting one of said bit line precharge means; a plurality of input-output buses, each connected to a single one of said bit line groups, respectively; a second select means for selecting one of said input-output buses; a plurality of means each for individually precharging a single one of said input-output buses; and third select means for controlling which of said input-output bus precharging means is operative.

Claim 18

A semiconductor integrated memory device comprising: a plurality of bit lines; a plurality of memory cells each connected to at least one of said bit lines; means for addressing said memory cells; at least two precharge means, a predetermined group of said bit lines being connected to each of said precharge means, respectively, said precharge means for precharging the associated group of said bit lines to an initial level; first select means for selecting one of said bit line precharge means; a plurality of input-output buses, each connected to a single one of said bit line groups, respectively; a second select means for selecting one of said input-output buses; a plurality of means each for individually precharging a single one of said input-output buses; and third select means for controlling which of said input-output bus precharging means is operative.

Claim 19

The semiconductor integrated memory device according to claim 14 further comprising an input-output circuit connected to said input-output buses through said second select means.

Claim 20

The semiconductor integrated memory device according to claim 14 or 15 further comprising: a plurality of sense amplifying means each for amplifying signals on a single one of said groups of bit lines, respectively; and fourth select means for selectively enabling one of said sense amplifying means.

Claim 21

The semiconductor integrated memory device according to claim 14 or 15 wherein said first, second and third select means are controlled by a select control signal.

Claim 22

The semiconductor integrated memory device according to claim 17 wherein said select control signal corresponds to signals for addressing said device.

Claim 23

The semiconductor integrated memory device according to claim 18 wherein said address signals are column address signals.

Claim 24

The semiconductor integrated memory device according to claim 18 wherein the address signals are row address signals.

Claim 25

A semiconductor integrated memory device comprising: a plurality of bit lines and row lines; row decoder means for selectively energizing said row lines; a plurality of memory cells, each connected to at least one of said bit lines and controlled by one of said row lines; at least two precharge means, each connected to a group of said bit lines for precharging said bit lines in said groups to an initial level, each of said precharge means being controlled by precharge control lines; first select means for selecting one of said precharge control lines; a plurality of input-output lines each connected to a single one of said bit line groups; a plurality of input-output line precharging means each associated with a single one of said input-output lines for precharging said input-output lines; second select means for selecting one of said input-output lines; third select means for selecting one of said input-output line precharge means; a select control signal line connected to said first, second and third select means; sense amplifier circuits, at least one operative with each of said bit line groups; an enable control line associated with each of said sense amplifier circuits; and fourth select means for selection of said sense amplifier circuit enable control lines.

Claim 26

A semiconductor integrated memory device comprising: a plurality of bit lines and row lines; row decoder means for selectively energizing said row lines; a plurality of memory cells, each connected to at least one of said bit lines and controlled by one of said row lines; at least two precharge means, each connected to a group of said bit lines for precharging said bit lines in said groups to an initial level, each of said precharge means being controlled by precharge control lines; first select means for selecting one of said precharge control lines; a plurality of input-output lines each connected to a single one of said bit line groups; a plurality of input-output line precharging means each associated with a single one of said input-output lines for precharging said input-output lines; second select means for selecting one of said input-output lines; third select means for selecting one of said input-output line precharge means; a select control signal line connected to said first, second and third select means; sense amplifier circuits, at least one operative with each of said bit line groups; an enable control line associated with each of said sense amplifier circuits; and fourth select means for selection of said sense amplifier circuit enable control lines.