Semiconductor memory read/write access circuit and method

Claim 1

A read/write circuit for a dynamic field effect transistor memory system including a matrix of dynamic storage cells, each storage cell having a capacitive storage node capable of being coupled to a column line in response to an addressable row selection means, a plurality of pre-amplifiers connected to said column lines for detecting and amplifying signals coupled to said column lines by said row selection means and at least one input/output terminal capable of being coupled to at least some of said column lines by the current conducting terminals of a field effect transistor switching means, the improvement comprising: column line precharging means for precharging said column lines to a predetermined first reference potential corresponding to a first stored logic state; input/output terminal precharging means for precharging said input/output terminal to a second predetermined reference potential having a magnitude less than said first reference potential by more than one field-effect transistor threshold voltage drop and greater than a potential corresponding to a second logic state; and addressable column selection means coupled to the gate electrode of said switching means for selectively applying a third reference potential to at least one of said switching means, said third reference potential having a magnitude not greater than one field effect threshold voltage drop above said second reference potential, whereby said field-effect transistor switching means will become conductive when the potential of a data signal to be coupled between a selected on of said column lines and said input/output terminal has a magnitude of less than one field-effect transistor threshold drop below said third reference potential.